Feb 2024 – Sep 2024 · 7 mos

Mar 2019 – Feb 2024 · 4 yrs 11 mos

• Led the architecture, design and verification of multiple IPs used in Silicon Lifecycle
• Monitoring (SLM). Specific IPs worked on: High Speed Access and Test (HSAT) and
• Signal Integrity Monitor (SIM). HSAT provides a framework to run manufacturing tests (ATPG
• patterns) in a System Level Test (SLT) or In-System Test (IST) in addition to traditional ATE. It
• uses High-Speed functional interfaces like PCIe or USB to deliver test content. SIM provides
• a mechanism for monitoring high-speed, forwarded clock double data rate interfaces like the
• UCIe.
• ● Architecture of the IP and overall solution architecture
• ● Verification architecture, design and implementation of stand-alone, as well as system
• level environments to verify functionality of HSAT
• ● Customer discussions leading to deployment of HSAT IP in their SOCs
• ● Eco-system partner discussions to help develop infra-structure to support HSAT IP solution
• ● Define feature set and ongoing enhancements of SLM IPs
• ● Provide guidance for debug on FPGA demo platform, analyze system level issues

Nov 2017 – Mar 2019 · 1 yr 4 mos

• ● Silicon bring-up and debug support
• ● Interact with sensor vendors to communicate/debug issues seen with sensor interfaces
• ● Interact with SoC vendor to debug FW/HW issues in SoC, enhance their verification
• models/environment to reproduce issues seen
• ● Third party IP vendor interaction for verification and validation.
• ● Review design, verification test plan and coverage reports of custom IP

Feb 2012 – Nov 2017 · 5 yrs 9 mos

• ● Manage verification engineering team, providing technical leadership and mentoring
• ● Design verification environment, models & checkers, test plans for full-chip/system verification
• ● Flexible environment and tests re-usable at full-chip/system or block level (for critical blocks).
• ● Interface with customers to port & run Golden Vector tests developed on other platforms
• (for example - Matlab) to cross-verify the system
• ● Using coverage metrics to find uncovered areas and add tests for those scenarios
• ● Setup, run and debug Gate level sims with timing
• ● Bring-up support – provide init sequences, debug and resolve issues, recreate potential
• issues in sims for debug

Jan 2006 – Jan 2012 · 6 yrs

• ● Design of verification environment, test plans and models/checkers for system verification
• ● Mechanisms for injecting vectors from Golden Reference models and comparing outputs

Jan 2005 – Jan 2006 · 1 yr

Jan 2003 – Jan 2005 · 2 yrs

• ● Development of test plans, verification strategy & components (transaction generators,
• checkers).
• ● Developing new tests and debugging RTL at module and system level.
• ● Managing collateral and legacy tests from cross – site teams.
• ● Providing inputs for performance optimization in cache coherence protocol.

Jan 1998 – Jan 2001 · 3 yrs