Aishwarya R — Software Engineer
Passionate VLSI RTL Design Engineer with hands-on experience in front-end digital design, verification, and integration. Skilled in developing RTL modules using Verilog/System Verilog and optimizing designs for performance, power, and area. Experienced in AXI-based interface design, timing closure, and synthesis flows. I enjoy solving complex digital design challenges and collaborating across teams to build reliable, high-performance silicon solutions.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in digital electronics and verification methodologies.
Location: Mysore, Karnataka, India
Experience: 2 yrs 11 mos
Skills
- Digital Electronics
Career Highlights
- Expert in VLSI RTL design and optimization.
- Hands-on experience with Verilog and System Verilog.
- Strong background in digital design verification.
Work Experience
Chipspirit
RTL Design Engineer (1 yr 11 mos)
Design Verification intern (4 mos)
Maven Silicon
Advanced VLSI design & Verification (1 yr)
Education
Bachelor of Engineering - BE at ATME College of Engineering, Mysuru
PUC at BGS Science PU College
10th at Nirmala English High School
