Ankit Agarwal

CEO

Bengaluru, Karnataka, India14 yrs 8 mos experience

Key Highlights

14+ years in ASIC and SOC Verification
Expertise in UVM and System Verilog
Strong leadership in cross-functional teams

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in ASIC and SOC validation.

Contact

Skills

Core Skills

Soc ValidationIp VerificationAi Soc VerificationSystem On A Chip (soc)Function VerificationAtm VerificationSubsystem Verification

Other Skills

Emulation Based VerificationCross-functional Team LeadershipLeading Development TeamsSilicon BringupSilicon ValidationKey Performance IndicatorsCache ManagementNeural NetworksCoding StandardsSignalMicrosoft PowerPointSemiconductor IndustryATEMicrosoft ExcelSVA

About

Experienced Hardware Engineer with a demonstrated history of working in the semiconductors industry with over 14+ years of experience in ASIC, IP, Sub Systems, SOC Verification. Skilled in System Verilog, Universal Verification Methodology (UVM), Python, C++, Organic Electronics, and Semiconductor Device. Strong media and communication professional with a Bachelors and Masters focused in Electronics and VLSI from IIT, Kanpur. Worked on full stacks of High Speed Peripherals like (PCIe, NVMe, RoCE, NVMeOF) for Flash Memories targeting client and server segments, USB, image processors hardware verification (IP/System), ATM Verification and ATE Vectors for Post Silicon Hands on experience of complete cycle of IP/System Verification - Planning, Execution, Risk Management, Sign Off.

Experience

14 yrs 8 mos

Total Experience

Average Tenure

Current Experience

Microsoft

2 roles

Principal DV Engineer

Promoted

Sep 2025 – Present · 9 mos

IP VerificationSub System VerificationSOC ValidationEmulation Based VerificationCross-functional Team LeadershipLeading Development Teams+2

Senior Design Verification Engineer

Jun 2023 – Sep 2025 · 2 yrs 3 mos

AI SOC Verification

Key Performance IndicatorsCache ManagementNeural NetworksCoding StandardsSignalAI SOC Verification

Texas instruments

System Design Verification Manager

Jan 2022 – May 2023 · 1 yr 4 mos · Bengaluru, Karnataka, India

System on a Chip (SoC)Microsoft PowerPointKey Performance IndicatorsSemiconductor IndustryATEMicrosoft Excel+13

Intel corporation

Senior Verification Engineer - Imaging and Camera Group, EGI

Jan 2018 – Jan 2022 · 4 yrs · Bengaluru, Karnataka, India

ASIC IP | SOC | DFT | Subsystem Verification
SOC Full Chip – ATM Verification and ATE Production Test Vectors
> Defining the strategy, environment, task planning, risk management, proposing mitigations
> ATM – Analog Test Mode verification for various Analog Phy IPs like USB, PCIe, DDR, MIPI, OTP, CCU, HTOL
> ATE – Automatic Test Equipment vector generation and vector verification for Post Si Production Testing
SOC – IP, Subsystem, Full Chip Verification
> Owning complete USB Subsystem Verification for SOC including USB Controller, USB3 Type C Phy and USB 2 Phy
> Integrating USB-SV based USB2/3 VIP (Synopsys) to verify USB2/3 device IP (Controller + Phy) for SOC requirement
> Written the SW Flow (SV-UVM FW Driver) to activate the IP and process control/data flows, interrupts, events
> Developing/Porting tests to ensure right generation / integration of USB IP core according to the architectural requirements
> Working with architect, designer, system team, software team from different geographies to validate customer use cases

Samsung electronics

2 roles

Techincal Lead Engineer

Oct 2014 – Jan 2018 · 3 yrs 3 mos

> PCI-E, PCIe Gen 1/2 /3 host side VIP development including all the layers(TL,DL,PL) to verify PCIe Gen 1/2/3 based devices
> RoCE IBT, RDMA Host Controller Verification Modelling meant for Ethernet Based SSDs
> System Verification consisting of PCIe, NVMe, Flash Memory System

Microsoft PowerPointKey Performance IndicatorsSemiconductor IndustryMicrosoft ExcelSVACommunication+8

Senior Hardware Engineer

Jul 2013 – Sep 2014 · 1 yr 2 mos

Host side PCIe VIP Development

Microsoft PowerPointKey Performance IndicatorsSemiconductor IndustryMicrosoft ExcelSVACommunication+8

Avanti fellows

Mentorship Manager

May 2012 – May 2013 · 1 yr · Kanpur

Monitoring and mentoring fellows, guiding the mentors to handle the issues of the fellows.

Microsoft PowerPointCommunicationProblem SolvingEnglish

Indian institute of technology, kanpur

M.Tech Thesis : Transmission Line Modelling of Source Resistance in Top Contact Organic TFT's

Jul 2011 – Jun 2013 · 1 yr 11 mos · IIT Kanpur

> Designed a C based 1-D simulator for simulating single layer organic device like diodes, incorporating various models in it
> Used the simulator along with Microcap simulations to extract source resistance of OTFT's
> Simulator allowed to study and analyze dependence of sourrce resistance on various parameters
> Computational time is reduced to a great extent as compared to existing device simulators

Microsoft PowerPointCommunicationProblem SolvingEnglish

Universiti teknologi malaysia

Summer Intern : Low Voltage Analog IC Design:

May 2011 – Jul 2011 · 2 mos · Johor Bahru, Malaysia

> Analyzed two stage Op-Amp to achieve considerable reduction in its power dissipation using Bulk Driven Technique.
> Achieved 44% decrease in power dissipation using this technique
> Valuable for low power IC design used in applications like hearing aids, implantable cardiac pacemakers

Microsoft PowerPointCommunicationProblem SolvingEnglish