Dhanuj Kumar Sharma — Software Engineer
Experienced SoC RTL Design Engineer skilled in Verilog RTL with foundational knowledge of AMBA protocols (APB, AHB and AXI) and DDR Protocol. Integrated LPDDR5 IP (Synopsys) and peripheral IPs for radar SoCs, ensuring timely tape out with sign-offs such as CDC, Linting, and RDC. Published researcher with a notable contribution in the field of "Voltage Conveyors", featured in Springer publication. Consistently pursuing opportunities to grow, learn, and excel in my field.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in SoC integration and memory protocols.
Location: Bengaluru, Karnataka, India
Experience: 3 yrs 10 mos
Skills
- Soc Integration
- Lpddr5 Integration
- Verilog
- Asic Design Methodology
Career Highlights
- Expert in SoC RTL Design with Verilog.
- Integrated LPDDR5 IP for radar SoCs.
- Published researcher in Voltage Conveyors.
Work Experience
Intel Corporation
Graphics Hardware Engineer (2 yrs 2 mos)
NXP Semiconductors
Design Engineer (1 yr 8 mos)
Student Intern (5 mos)
Webtek Labs Pvt. Ltd.
Trainee (1 mo)
Aedifico Tech Pvt. Ltd.
Trainee (1 mo)
Education
Master of Technology - MTech at Netaji Subhas University of Technology
Bachelor of Technology - BTech at Guru Gobind Singh Indraprastha University