YERRA RAJESH

Product Engineer

Bengaluru, Karnataka, India7 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL Design and SoC Integration.
Recognized for contributions in RTL Insertion and Debug.
Strong background in multiple protocol designs.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and SoC integration.

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Skills

Core Skills

Rtl DevelopmentSoc Integration

Other Skills

RTL CodingRTL LintUPFVCLP Subsystem/SOC IntegrationCDCSynthesisDefactoSDC ConstraintsCaliberRTL quality checksPCIe registersSecurity and RASSystem VerilogMilestone checklistPerl

About

1. I started working as SOC Design Engineer at Intel in the PCIe domain (Knowledge: RTL Design, integration and Quality checks in PCIE subsystem) 2. Experience in Protocol Bridges RTL Design (Protocol Knowledge: CXL, PCIE, UCIe, AMBA etc...) 3. Knowlege on LINT, Power Artist, FEV, Caliber, CDC, VCLP, Defacto, Collage, Quartus Prime, FC, DFT. 4. Experienced in front-end digital design and verification of an IP/SoC besides SoC integration, validation, and post-silicon bring-up. Involved in all aspects of several IPs integration and features definition to RTL coding, verification, synthesis. 5. Recognitions received at the Team level and Business Unit level for the contributions towards RTL Insertion and Debug. 6. MTech focused on Communication Engineering from IIT Guwahati. B.Tech in Electronics & Communication at IIIT-RGUKT Nuzvid.

Experience

7 yrs

Total Experience

3 yrs 6 mos

Average Tenure

5 yrs 11 mos

Current Experience

Intel corporation

SOC Design Engineer

Jul 2020 – Present · 5 yrs 11 mos · Bengaluru, Karnataka, India · Hybrid

I started working as SOC Design Engineer at Intel in the PCIe domain.
Worked on Front-End RTL Design/Integration on interfaces like PCIe, CXL, and UCIe, with three years
focused on the PCIe subsystem for discrete graphics SOCs.
Worked on Protocol Bridges(iCXL2UFI) RTL design, Integration, and architecture.
Knowledge of AMBA protocols (APB, AHB, AXI, CHI). I worked on a couple of projects where these AMBA
protocols were used.
Strong knowledge of Different Industry Tools -Power Artist, Spyglass Lint, VCS, CDC, LEC, Verdi, VCLP, Defacto, Collage, Quartus Prime, FC, SGDFT
Functional debugging, worked with the Verification team to define review test plans and coverage
analysis.
I worked for different SoCs, from 0P0 to Power On.
Proposed and implemented extra release checks at the subsystem level and added additional
automation scripts to the gatekeeper to increase the Quality of the Release.
Responsible for debugging and fixing the issues at IP and SoC levels and working with Verification
Team to improve the coverage of IPs.
Skills: RTL Coding · RTL Lint · UPF · VCLP Subsystem/SOC Integration · CDC · Synthesis · Defacto · SDC Constraints · Caliber · RTL quality checks· PCIe registers· Security and RAS· System Verilog· Milestone checklist· Perl· Python· Firmware· RDL, DFT, Timing

RTL CodingRTL LintUPFVCLP Subsystem/SOC IntegrationCDCSynthesis+16

Indian institute of technology, guwahati

Teaching Assistant

Jun 2019 – Jul 2020 · 1 yr 1 mo · Guwahati, Assam, India

I was the master's student representative in Student Academic Board at IIT Guwahati. During my tenure, I attended department meetings and acted as a mentor for graduate students.