Meghvern Pathak

Software Engineer

New Delhi, Delhi, India4 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in digital design verification for high-speed interfaces.
Proficient in UVM and SystemVerilog methodologies.
Strong background in VLSI and circuit design.

Stackforce AI infers this person is a Digital Design Verification Engineer specializing in semiconductor technologies.

Contact

Skills

Core Skills

Digital Circuit DesignUvm

Other Skills

AssertionsDebuggingpython scriptingScriptingZebuVerilogSystemVerilogDVEVerdiVCSTurbo CodesError Correcting CodesXilinx VivadoSymicaDEAnalog Circuit Design

About

Hi there! I am working as a digital design verification engineer at Synopsys Inc. India.

Experience

4 yrs 10 mos

Total Experience

2 yrs 5 mos

Average Tenure

3 yrs 11 mos

Current Experience

Synopsys inc

2 roles

ASIC Digital Design, Sr Engineer

Promoted

Dec 2024 – Present · 1 yr 6 mos

Contributing as a functional verification engineer for the High-Speed Interface IP team, SG Group.
Working on high-speed multi-protocol SerDes IPs.

AssertionsDebuggingpython scriptingScriptingZebuVerilog+18

ASIC Digital Design, Engineer

Jul 2022 – Dec 2024 · 2 yrs 5 mos

• Work concerns digital design verification of protocol-based SerDes IPs: 1. HDMI/DP (PCS level) 2. MPHY (PHY level) using standard SV and UVM testbench modelling.

UVMVCSDigital Circuit Design

Intel corporation

Graduate Intern Technical

Jun 2021 – Jun 2022 · 1 yr · Bangalore Urban, Karnataka, India

Contributed as a functional verification engineer for the ICG team.
Work involved performing design verification and feature additions w.r.t the Camera Serial Interface (CSI) protocol to the UVM TB for the implemented input system module in the latest Image Processing Unit (IPU) IP.

UVMVCSDigital Circuit Design