saiteja vinnakota

Software Engineer

West Godavari, Andhra Pradesh, India7 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in ASIC Physical Design and Timing Closure.
  • Proficient in Static Timing Analysis and Low-power Design.
  • Strong background in Floorplanning and Place & Route.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC Physical Design.

Contact

LinkedIn

Skills

Core Skills

Timing ClosureStatic Timing Analysis

Other Skills

Low-power DesignFloorplanningPlace & RoutePerlTCLShell Scripting

Experience

7 yrs 10 mos
Total Experience
1 yr 11 mos
Average Tenure
4 yrs 7 mos
Current Experience

Synopsys inc

ASIC Physical Design Engineer

Nov 2021 – Present · 4 yrs 7 mos · Hyderabad, Telangana, India

Timing ClosureStatic Timing AnalysisLow-power DesignFloorplanningPlace & RoutePerl+2

Invecas

Physical Design Engineer

Feb 2020 – Oct 2021 · 1 yr 8 mos · Hyderabad, Telangana, India

Soctronics technologies private limited

Physical Design Engineer

Nov 2018 – Jan 2020 · 1 yr 2 mos · Greater Hyderabad Area

Veda iit

Trainee

May 2018 – Oct 2018 · 5 mos · Greater Hyderabad Area

  • Trained in Physical Design Domain , VLSI

Education

Bapatla Engineering College

Bachelor of Technology — Electronics and Communications Engineering

Jan 2014 – Jan 2018

Sri Chaitanya College of Education

Intermediate — MPC

Jan 2012 – Jan 2014

Aditya Public School - India

7 - 10 — High School

Jan 2008 – Jan 2012

Sun Shine School

KG - 6 — Schooling

Jan 2000 – Jan 2008

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