Rakshith G N — Product Engineer
Experience : • Experience in handling SERDES PHY, PCIE Analog layout design blocks such as TX-LDO, op-amp, Current Mirror, Bias blocks, power gate and custom digital cell layout designs. • Experience on block level placement, Routing, Physical verification checks etc. • Strong exposure on Analog matching techniques, elimination of latch-up, shielding, area optimization, EM, SH, IR drop and RV issues. • Experience in Deep sub micron technologies like TSMC 3nm, TSMC 5nm, Intel 7nm, 10nm,14nm. • Good experience in Physical verification areas like DRC, LVS, ERC, Antenna checks. • Tools Exposure: Cadence Virtuoso EXL , XL and L, Schematic Editor, CPDS for Physical Verification. ….Thanks & Regards…. Rakshith G N Email:- rakshithgn17@gmail.com Direct : +91-8792747104
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog layout and Physical verification.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 8 mos
Skills
- Analog Layout Design
- Physical Verification
Career Highlights
- Expert in Analog layout design and verification.
- Proficient in Deep sub micron technologies.
- Strong skills in Physical verification and optimization.
Work Experience
IBM
Lead Analog Layout Designer (1 yr 8 mos)
Synopsys Inc
Staff A&MS Layout Design (8 mos)
A&MS Layout Design Engr, Sr I (1 yr 10 mos)
SmartPlay Technologies - An Aricent Company
Engineer (4 yrs 6 mos)
Education
Bachelor's degree at Visvesvaraya Technological University
Pre university at Seshadripuram First Grade College (S.F.G.C), Bengaluru
