sumeet rathore

Product Engineer

Hyderabad, Telangana, India4 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Achieved 100% code and functional coverage closure.
Enhanced M-PHY UVM testbench for feature migration.
Collaborated effectively with design teams for validation.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification methodologies.

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Skills

Core Skills

Design Verification TestingFunctional Verification

Other Skills

VerilogCommunicationUniversal Verification Methodology (UVM)Problem SolvingInterpersonal CommunicationDebuggingM-PHY IPStructured Verification PlansGate-Level SimulationPower State Table CoverageUVM TestbenchFunctional Coverage ModelsProtocol-Level AssertionsTest CasesM-PHY Protocol

About

Currently contributing to Synopsys Inc. as an ASIC Design Verification Engineer, focusing on the verification and enhancement of M-PHY IP testbenches. Played a key role in developing and verifying the H8ULP feature, achieving full code and functional coverage closure through structured verification plans. Collaborated with design teams to execute gate-level simulations, resolve timing violations, and attain functional and timing closure. Graduated with a B.Tech in Electronics from Birla Vishvakarma Mahavidyalaya and in Electrical and Electronics Engineering from Gujarat Technological University. Proficient in RTL and functional verification, with hands-on experience in SystemVerilog, UVM, and Verilog. Dedicated to advancing semiconductor solutions through methodical verification techniques and team collaboration.

Experience

4 yrs 9 mos

Total Experience

2 yrs 4 mos

Average Tenure

3 yrs 9 mos

Current Experience

Synopsys inc

4 roles

ASIC Design Engineer,I

Jul 2023 – Present · 2 yrs 11 mos

VerilogCommunicationUniversal Verification Methodology (UVM)Problem SolvingInterpersonal CommunicationDebugging+2

asic design verification engineer

Jul 2023 – Present · 2 yrs 11 mos

Focused on verification and enhancements of Synopsys M-PHY IP (V5) testbench.
Successfully developed and verified the H8ULP feature using a structured verification plan, achieving completion of all targeted metrics, including test cases, scenarios, and 100% code and functional coverage closure.
Executed gate-level simulation (GLS) for the M-PHY IP testbench, reporting design issues and resolving timing violations to achieve functional and timing closure.
Created and executed power state table(UPF) coverage plans using structured vPlans, achieving 100% power state table coverage closure.
Collaborated with design teams to analyze the M-PHY V6 specification and architecture, and developed detailed verification and coverage plans, ensuring complete feature validation and coverage closure.
Played a key role in enhancing and extending the M-PHY V5 UVM testbench for M-PHY V6 migration, incorporating new features such as datapath, test mode, EyeMon, H8ULP, and adaptation.
Developed functional coverage models, protocol-level assertions, and new testcases for M-PHY V6, ensuring thorough feature validation and verification completeness.

M-PHY IPStructured Verification PlansGate-Level SimulationPower State Table CoverageUVM TestbenchFunctional Coverage Models+4

Intern

Sep 2022 – Jul 2023 · 10 mos

VLSI Verification engineer

VerilogCommunicationUniversal Verification Methodology (UVM)Problem SolvingInterpersonal CommunicationDebugging

Asic design verification engineer, intern

Sep 2022 – Jul 2023 · 10 mos

Acquired a strong understanding of the M-PHY protocol and applied it in IP verification activities.
Worked on the Synopsys M-PHY IP UVM-based testbench, contributing to improvement in efficiency and reusability.
Developed and executed coverage plans, ensuring 100% functional feature and corner-case verification through structured vPlans.
Contributed towards achieving >95% code coverage and 100% assertion coverage, accelerating verification closure.
Developed new test scenarios and assertions, strengthening functional coverage and validating corner cases.
Executed proactive debugging of top-level regressions, resulting in a substantial reduction of critical bugs and improved design stability.

M-PHY ProtocolUVM TestbenchCoverage PlansDebuggingDesign Verification Testing

Maven silicon

2 roles

VLSI Design & Verification engineer

Apr 2021 – Dec 2022 · 1 yr 8 mos

Design Internship

Apr 2021 – Apr 2022 · 1 yr

Proficient in Verilog, SystemVerilog, UVM methodology, and assertion verification
Contributed to AHB-to-APB bridge and AXI protocol verification projects, ensuring protocol compliance and functional correctness.
Hands-on experience in test planning, testcase development, functional coverage, and code coverage analysis.

VerilogSystemVerilogUVM MethodologyAssertion VerificationTest PlanningTestcase Development+1