RISHABH SRIVASTAVA — Software Engineer
Digital Design Engineer, with 3 years of experience both in ASIC and FPGA. Currently working with Synopsys. Decent exposure in RTL and firmware design in SERDES PHY IPs along with debugging and reviewing digital and mixed signal waveforms. Hands on experience with Pre Silicon Validation of soft IPs for USB3/USB4 based PHYs on FPGA. Responsible for delivering simulation models, synthesis/timing closure and FPGA prototyping. Currently working on FPGA development and simulation support for PCIE6 based PHY prototyping. Equipped with decent problem solving and team work skills.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and FPGA technologies.
Location: Delhi, India
Experience: 7 yrs
Skills
- Asic Design
- Fpga Development
Career Highlights
- 3 years of experience in ASIC and FPGA design
- Expertise in SERDES PHY IPs and USB3/USB4 validation
- Strong problem-solving and teamwork skills
Work Experience
Synopsys Inc
Asic Digital Design Engineer Sr. 1 (3 yrs 4 mos)
Asic Digital Design Engineer 2 (2 yrs 3 mos)
Asic Digital Design Engineer 1 (1 yr 5 mos)
Education
Bachelor of Engineering - BE at Netaji Subhas Institute of Technology