Sandeep valavala

Product Engineer

Andhra Pradesh, India4 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Chip-Level and Block-Level Place and Route implementation.
Led Transparent Hierarchy Optimization for enhanced QoR.
Proven track record in timing closure and optimization.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Place & Route.

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Skills

Core Skills

Place & RoutePhysical Design

Other Skills

Chip-Level Place and RouteBlock-Level Place and RouteSynthesisRoutingClock Tree SynthesisTransparent Hierarchy OptimizationI/O Delay ManagementPin PlacementTiming ClosureFloorplan ImplementationStandard Cell PlacementRouting OptimizationSPEF GenerationECO CreationPrime time

About

As a Senior Product Engineer at Synopsys, I specialize in Chip-Level and Block-Level Place and Route (PnR) implementation. I have over 4 years of experience in this role, where I am responsible for implementing the entire PnR flow, from synthesis to routing, including placement, clock tree synthesis (CTS), and routing at both the top and block levels. I also lead the implementation of the Transparent Hierarchy Optimization (THO) flow at the top level to enhance placement and routing, ensuring better Quality of Results (QoR) convergence at the top. Additionally, I manage the rebudgeting of I/O delays after each stage to optimize interface convergence at the top level. Prior to joining Synopsys, I worked as an Application Engineer at L&T Technology Services Limited, where I implemented floorplan by placing macros and ports, executed standard cell placement, led the implementation of CTS, managed routing and post-route optimization, generated SPEF files using StarRC, and created ECOs for signoff timing closure across all scenarios using PrimeTime. I hold a Bachelor of Technology degree in Electronics and Communication Engineering from Amrita School of Engineering. I am passionate about delivering high-quality solutions that meet the needs of my clients and contribute to the advancement of the field of VLSI design.

Experience

4 yrs 5 mos

Total Experience

2 yrs 2 mos

Average Tenure

3 yrs 11 mos

Current Experience

Synopsys inc

2 roles

Senior Engineer

Promoted

Jan 2024 – Present · 2 yrs 5 mos · Bengaluru, Karnataka, India

Currently serving as a Senior Product Engineer (PE) at Synopsys, specializing in Chip-Level and Block-
Level Place and Route (PnR) implementation.
o Responsible for implementing the entire PnR flow, from synthesis to routing, including placement, clock
tree synthesis (CTS), and routing at both the top and block levels.
o Lead the implementation of the Transparent Hierarchy Optimization (THO) flow at the top level to enhance
placement and routing, ensuring better Quality of Results (QoR) convergence at the top.
o Manage the rebudgeting of I/O delays after each stage to optimize interface convergence at the top level.
o Create block abstracts at the block level and integrate them into the top-level design, followed by clock
mapping and constraint mapping between top and block levels.
o Oversee interface timing closure at the sub-block level to ensure optimal performance.
o Implement hierarchical pin assignment (pin placement), including feedthrough insertion, bundle pin
placement, and pin detour analysis at the hierarchical level

Chip-Level Place and RouteBlock-Level Place and RouteSynthesisRoutingClock Tree SynthesisTransparent Hierarchy Optimization+5

Application Engineer I

Jul 2022 – Jan 2024 · 1 yr 6 mos · Bengaluru, Karnataka, India

Place & Route

L&t technology services limited

Physical Design Engineer

Dec 2021 – Jun 2022 · 6 mos · Mysuru, Karnataka, India

o Implemented floorplan by placing macros and ports, along with physical-only cell insertion, while
minimizing congestion.
o Executed standard cell placement, iteratively resolving congestion and setup violations to achieve optimal
results.
o Led the implementation of clock tree synthesis (CTS), focusing on meeting target skew and latency
requirements with respect to PPA (Power, Performance, Area).
o Managed routing and post-route optimization to achieve the best PPA, while concurrently addressing
shorts and opens.
o Generated SPEF files using StarRC for accurate parasitic estimation.
o Created ECOs (Engineering Change Orders) for signoff timing closure across all scenarios using
PrimeTime.