Jatin Agarwal

Software Engineer

Noida, Uttar Pradesh, India3 yrs 11 mos experience

Highly Stable

Key Highlights

Experienced in Clock Domain Crossing and Lint.
Strong foundation in Electronics and Communications Engineering.
Proficient in multiple programming languages including C++ and Python.

Stackforce AI infers this person is a VLSI Engineer with expertise in digital design and verification.

Contact

Skills

Core Skills

Clock Domain Crossing

Other Skills

LintRDCReset Domain CrossingLinuxC++VerilogDigital ElectronicsData StructuresC (Programming Language)Python (Programming Language)Microsoft OfficeSystemVerilogStatic Timing AnalysisCDCRobot Operating System (ROS)

Experience

3 yrs 11 mos

Total Experience

3 yrs 8 mos

Average Tenure

3 mos

Current Experience

Siemens eda (siemens digital industries software)

Corporate Application Engineer

Mar 2026 – Present · 3 mos · Noida · Hybrid

Clock Domain CrossingLint

Synopsys inc

3 roles

Validation/Verification Sr Engineer

Dec 2024 – Mar 2026 · 1 yr 3 mos

Validation Engineer

Jul 2022 – Dec 2024 · 2 yrs 5 mos

Intern

Mar 2022 – Jun 2022 · 3 mos

3st technologies

VLSI

Feb 2021 – Jan 2022 · 11 mos · India

Education

Bharati Vidyapeeth's College Of Engineering New Delhi

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2018 – Jan 2022

Greenfields Public School - Dilashad Garden

12 — Mathematics and Computer Science

Jan 2006 – Jan 2018

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