Lokesh Mistry

Software Engineer

Ahmedabad, Gujarat, India9 yrs 7 mos experience

Highly Stable

Key Highlights

8+ years in FPGA/IP Verification and Validation
Expertise in UVM and DO-254 standards
Proficient in USB 2.0 Protocol and verification methodologies

Stackforce AI infers this person is a highly skilled ASIC/FPGA Verification Engineer with extensive experience in safety-critical avionics.

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Skills

Core Skills

AsicFpgaUvm

Other Skills

Perspec R&DPerspec Verifier toolSLN/PSS LanguageCache coherencyPCIeCHIAXIUSB2.0 VIP IntegrationScoreboard implementationSVFunctional VerificationDO-254Designing verification componentsDeveloping Test proceduresImplementing assertions

About

8+ Years of Experience In FPGA/IP Verification (UVM) and Validation of Complex FPGA Designs with Design Assurance Level (DAL A) As Per DO-254 standards, which Is applied for highest safety critical Airborne Electronic Hardware. Summary • Extensive experience in Design Verification • In-depth knowledge of a UVM, System Verilog, HDL, constrained verification, Assertions • Knowledge of Avionics Standards for Complex Electronic Hardware like DO-254 • Knowledge of the tools like DOORs, VCS Verdi, Questasim. • Profound knowledge of USB 2.0 Protocol • Profound knowledge of enforcing test cases, simulation and verification methodology • Outlining test and coverage plans, verification field and debugging firmware • Skilled in writing test plans, coverage plans, and debugging RTL

Experience

9 yrs 7 mos

Total Experience

3 yrs 10 mos

Average Tenure

3 yrs 4 mos

Current Experience

Cadence design systems

Lead Software Engineer

Feb 2023 – Present · 3 yrs 4 mos · Ahmedabad, Gujarat, India

Perspec R&D
Perspec Verifier tool and coherency library.
SLN/PSS Language
Cache coherency
PCIe
CHI
AXI

Perspec R&DPerspec Verifier toolSLN/PSS LanguageCache coherencyPCIeCHI+3

Intel corporation

Senior ASIC Verification Engineer

Jul 2021 – Dec 2022 · 1 yr 5 mos

Contractor
Worked on the scoreboard implementation of several IP which includes IOSF primary and SB interface using SV and UVM.

Scoreboard implementationSVUVMASICFPGA

Alpha-numero

2 roles

Senior ASIC Verification Engineer

Promoted

Sep 2019 – Jan 2023 · 3 yrs 4 mos

Worked on the USB2.0 VIP Integration in processor based subsystem.
Worked on the scoreboard implementation of several IP which includes IOSF primary and SB interface using SV and UVM.

USB2.0 VIP IntegrationScoreboard implementationSVUVMASICFPGA

ASIC Verification Engineer

Sep 2016 – Aug 2019 · 2 yrs 11 mos

Functional Verification of FPGA's using methodologies UVM for the Advanced, Integrated Flight Control Electronics IFCE using DO-254 (Design Assurance Guidance for Airborne Electronic Hardware) Standard.
Review Each requirement enlisted, should be unambiguous, verifiable, detailed and devoid of conflicts with other design requirements.
Designing verification components such as Monitors, Scoreboards, Predictors.
Developing Test procedures and review to ensure that complete functionality has been achieved.
Implementing assertions, checkers and functional coverage based on Functional Requirement.
Analyzing and debugging simulation failures.
Documentation & Review in assessing areas that have been missed out or could be improved.
Standards : DO254