Sreesurya Aitha

Product Engineer

San Francisco, California, United States5 yrs 10 mos experience

Key Highlights

Expertise in Frontend VLSI Design and Computer Architecture
Proven track record in verification and validation processes
Strong leadership experience in organizing technical events

Stackforce AI infers this person is a Semiconductor Verification Engineer with a focus on VLSI and Computer Architecture.

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Skills

Core Skills

Computer ArchitectureVerification And Validation (v&v)LeadershipDigital Logic Design

Other Skills

RISC-VSystemVerilogPython (Programming Language)VerdiVerilogC++MakefileSynopsys toolsTest PlanningDebuggingShell Scriptinglearning agilityDigital ElectronicsUniversal Verification Methodology (UVM)Communication

About

Aspiring Frontend VLSI Engineer, achieving a dynamic and career oriented position in Semiconductor industry by utilizing my skills and abilities that offers professional growth while being resourceful, innovative and flexible. Having hands-on experience and profound knowledge in Emulation runtime Verification in ZEBU(Full emulation flow), RTL Coding using synthesizable constructs of Verilog, Advanced digital logic design, Static Timing analysis, Simulation, FSM based design, C,C++, System verilog EDA tools:- Xilinx Vivado, Synopsys-VCS,Verdi, Modelsim(Mentor Graphics),Questasim(Mentor Graphics). Passionate about Computer architecture & Frontend VLSI Design. ++ I personally believe that you can do anything you set your mind to, if you have the discipline to persevere when failure ensues (which it will) and an excitement that extends beyond doubt.

Experience

5 yrs 10 mos

Total Experience

Average Tenure

Current Experience

Tenstorrent

Architecture DV Intern

May 2026 – Present · 1 mo · Santa Clara, CA · On-site

RISC-VComputer ArchitectureSystemVerilog

Synopsys inc

3 roles

Senior Emulation Verification Engineer

Dec 2024 – Aug 2025 · 8 mos

Team:- Technology, and Product development group (Hardware-Assisted Verification).
Qualified Runtime–DMTCP feature across cross-functional multi-unit designs (Constellation, perf); conducted weak area testing and reproduced 200+ customer issues In-house.
Built an automated C++/zRci testbench generator and regression scripts to automate runtime test suite creation.

Python (Programming Language)VerdiVerification and Validation (V&V)SystemVerilogVerilogC++

Emulation Verification Engineer

May 2022 – Dec 2024 · 2 yrs 7 mos

Team: Verification group (System design Group -Hardware assisted Verification).
Performed pre-silicon verification using Synopsys ZEBU emulators (ZS4, ZS5); analyzed and debugged runtime issues across features such as ZEMI3, DMTCP, and SVA, and Runtime transactors.
Designed and executed test plans, unit-level test cases (C++/Verilog), and checkers integrated into regression workflows, successfully bring-up of new benchmarks with robust validation of runtime functionality/performance.
Automated routine runtime tasks, improving efficiency by 40%, and collaborated with the Runtime R&D team to reproduce customer issues and enhance in-house regressions, reducing emulation issues by 22%.
Owned L1 Convergence across all runtime features, and held ownership of the DMTCP end-to-end (validation, reproducing customer issues, continuous stress testing on benchmarks, and enhancements testing.

MakefileSynopsys toolsVerdiTest PlanningDebuggingSystemVerilog+4

Verification engineer Intern(Contractor)

Mar 2022 – Apr 2022 · 1 mo

Team: Verification group(SDG).

Induce-together toexplore™

2 roles

HR

May 2021 – Aug 2021 · 3 mos

Program Manager

Aug 2020 – Jun 2021 · 10 mos

A student community, where we provide Research and development related to student development in Engineering and related education.
We also collaborate with different industries and R&D to explore the knowledge of student by conducting many educational activities like hackathons,
Competitions,and also provide incubation support where innovative ideas can be developed into Real time products..

Lucid vlsi

RTL Design and verification

Jan 2021 – Mar 2021 · 2 mos

learning agility

The electronix club

2 roles

President

Aug 2020 – Jul 2021 · 11 mos

As the head of the club,we have organized various national level events such as quizathon,project expo's & innovative guest talks by different entrepreneurs & started Electronics specific domains & started conducting domain based sessions to our fellow students.
Domains:
VLSI
Embedded Systems
Networking & Communication.

Technical Deputy

Jan 2019 – Aug 2020 · 1 yr 7 mos

We conduct sessions for our fellow students of 100+ people in our Club to share knowledge about working of electronic components and latest technologies of ECE & helps in building on domain based projects.

Leadership

Internshala

2 roles

Internshala training captain

Aug 2019 – Sep 2019 · 1 mo

SystemVerilogVerilogDigital logic designDigital ElectronicsUniversal Verification Methodology (UVM)

INTERNSHALA STUDENT PARTNER ISP18

Jul 2019 – Aug 2019 · 1 mo

Communication

Bharat heavy electricals limited

CNC DEPARTMENT

Jul 2019 – Aug 2019 · 1 mo · Hyderabad, Telangana

i have done on cnc coding and industrial automation.where we have done various tool cutting operations using cnc coding and learned various concepts of gas turbines etc.,and learned on plc machines.