Judith Madhuri Sahaya Raj — Software Engineer
I have completed M.Eng. in Engineering Systems and Computing from The University of Guelph, Ontario. I am experienced in the Physical Design domain. I have ► Worked on the Physical Design convergence (Synthesis to Post-Route) of blocks. ► Handled blocks with cell count > 1M and maximum frequency of 1GHz. ► Worked on technologies - Intel 10nm++, 10nm, 7nm and TSMC 5nm. ► Hands on experience with tools - Design Compiler, ICC2, Fusion Compiler, Primetime, Caliber, FEV Conformal, VCLP, PTPX, RV. ► Have knowledge of programming languages - TCL, PERL and Python. ► Been a part of the Subsystem level timing team. ► Owned Calber at Subsystem level. Worked on Layout design using Cadence Virtuoso during Undergrad.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and VLSI technologies.
Location: Ottawa, Ontario, Canada
Experience: 2 yrs 7 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expertise in Physical Design for advanced semiconductor technologies.
- Hands-on experience with leading design tools and methodologies.
- Strong academic background with a 3.97 GPA in Engineering.
Work Experience
Synopsys Inc
ASIC Physical Design Engineer II (3 yrs 1 mo)
Intel Corporation
System-on-Chip Design Engineer (1 yr 3 mos)
Physical Design Engineer - Contract role (1 yr 4 mos)
Education
Master of Engineering - MEng at University of Guelph
Bachelor of Technology at Vidyavardhaka College of Engineering
