Jitendra Kumar — Product Engineer

Physical Design • Experienced working on 5nm tech node project. • Hand on experience in handling different EDA tools Innovus, PTPX and Voltus. • Implemented floor planning, power planning, placement, and routing using industry- standard EDA tools. • Good understanding of Static Timing Analysis. • Experienced with physical verification checks including design rule checks (DRC) and layout versus schematic (LVS) to ensure design compliance with process design rules and schematic intent. • Optimized design for timing, power, and area to meet project requirements and customer specifications. • Met all the deliverables on time and demonstrated strong problem-solving skills. • Have deep understanding of Physical Design flow (PnR) . Low Power - Methodology Engineer • Experienced working on low power estimation (for both vector-based and vector less) and optimization techniques. • Conducted comprehensive power analysis experiments, considering various factors including slew, load, and extraction corner updates. • Developed automation for vectorless power estimation, memory power analysis, and optimization, enhancing efficiency and accuracy. • Analyzed and debugged dynamic power issues, including low annotation of switching activity in vector-based power analysis.

Stackforce AI infers this person is a Low Power Design Engineer specializing in VLSI and semiconductor industries.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs