Karthik Patil

Product Engineer

Bengaluru, Karnataka, India3 yrs 11 mos experience

Key Highlights

Expert in AMS verification and behavioral modeling.
Proven track record in multi-protocol SerDes PHY verification.
Strong debugging skills in mixed-signal environments.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in AMS and SerDes technologies.

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Skills

Core Skills

Ams VerificationVerilog-amsSerdes VerificationFunctional Verification

Other Skills

analog modellingSerDesVerilogPython scriptingUSB3.0FundamentalsThinking SkillsReal Number modellingSVRNMAMBA AHBCode CoverageScriptingCadence VirtuosoSpyglassLinux

About

AMS Verification Engineer with experience in Co-Simulation, behavioral modeling, and verification of high-speed SerDes PHYs and memory interfaces. Worked on multi-protocol SerDes verification supporting PCIe, SATA, Ethernet, and CCIX, including PLL/CDR validation and PVT-corner analysis. Currently working on HBM verification. Hands-on experience in Verilog-AMS, SV-RNM, Wreal modeling, AMS assertions, and Model vs Schematic (MVS) validation for analog IPs including POR, SAR ADC, LDO, and VCO. Technical interests: AMS Verification, Behavioral Modeling, Verilog-AMS, UVM-MS, HBM/DDR, SerDes PHY, PLL/CDR, and Mixed-Signal SoC Verification.

Experience

3 yrs 11 mos

Total Experience

1 yr 7 mos

Average Tenure

7 mos

Current Experience

Iravan technologies

AMS Verification Engineer

Nov 2025 – Present · 7 mos · Pune City, Maharashtra, India · On-site

AMS Verification Engineer at IRAVAN Technologies, working on Analog Mixed-Signal (AMS) verification of high-speed and power management IPs at both block and system level. Experienced in developing and validating SystemVerilog RNM (SV-RNM) and Verilog-AMS behavioral models for analog components including ADC, LDO, VCO, and POR.
Skilled in performing Model vs Schematic (MVS) correlation across PVT corners to ensure alignment with transistor-level simulations. Proficient in building and executing AMS/UVM-based testbenches, incorporating assertions and self-checkers for robust functional and corner-case validation.
Hands-on experience in debugging mixed-signal issues using waveform analysis tools such as SimVision, with a strong focus on root-cause identification across analog and digital domains. Actively involved in co-simulation and system-level verification, enabling faster regression cycles and improved coverage through RNM methodologies.
Collaborating closely with design and integration teams to resolve functional, modeling, and convergence issues, while supporting large-scale regressions and verification closure in SoC environments.

Verilog-AMSanalog modellingAMS verification

Synopsys inc

AMS verification Engineer (GET)

Sep 2024 – Sep 2025 · 1 yr · Bengaluru, Karnataka, India · On-site

Worked on Highspeed SerDes PHY IP in IPG group at Synopsys.
Responsible for handling RTL and Analog verification, primarily between PCS and PMA of SerDes
Responsible for carrying out functional verification of multi-protocol SerDes PHY which supports PCIE (gen 1-5), SATA, Ethernet, CCIX and SGMI protocol.
Executed 50+ simulations across SS, TT, and FF corners for TX, RX, and support blocks, verifying functionality and extracting detailed power metrics for each block.
Performed GLS verification with SDF, ensuring timing and functional correctness.
Using the extracted netlist, developed the testbench and environment setup for various test cases such as data rate change, power analysis and FSM evaluation of the top-level module of the PHY

SerDesVerilogSerDes verificationfunctional verification