S

Sandeep Aranake

Software Engineer

Sunnyvale, California, United States34 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in electronic design automation for VLSI circuits
  • Proficient in low power system design and synthesis
  • Co-author of a patent and two publications
Stackforce AI infers this person is a VLSI design expert with a strong focus on EDA and FPGA technologies.

Contact

LinkedIn

Skills

Core Skills

EdaC++Cpu ArchitectureFpgaVerilog

Other Skills

Logic SynthesisSequential optimization techniquesLow power constraintsTiming and power analysisCObject Oriented DesignAlgorithm designCPU based hardware accelerationCycle based simulationNetlist partitioningRISC based CPU architectureDesign PatternsFPGA synthesisSoftware developmentWindows

About

I work in the area of electronic design automation (EDA) for VLSI circuits. Key area expertize: ★ Design and implementation of electronic systems ★ Scan synthesis ★ Simulation and verification of electronic system ★ System emulation using FPGAs ★ Parallel computing and its use in implementation, verification and emulation ★ Low power system design and synthesis Core strengths ★ Computer Algorithms ★ Digital design ★ Logic optimization ★ System performance analysis ★ Object Oriented Design ★ C and C++ ★ UML & Design Patterns ★ VHDL & Verilog ★ Two publications ★ Co-author of one patent

Experience

34 yrs 10 mos
Total Experience
6 yrs 11 mos
Average Tenure
21 yrs 10 mos
Current Experience

Synopsys

Software Engineer

Aug 2004 – Present · 21 yrs 10 mos · Mountain View, CA, USA

  • ★ Logic Synthesis, sequential optimization techniques such as retiming
  • ★ Synthesis under low power constraints, clock gating, UPF
  • ★ Timing and power analysis
  • ★ Experience in synthesis methodologies used in designing high end VLSI chips
  • ★ Design compiler, Power compiler, Prime Time
  • ★ C, C++, Object Oriented Design
  • ★ Algorithm design and implementation
  • ★ Scan synthesis
Logic SynthesisSequential optimization techniquesLow power constraintsTiming and power analysisCC+++3

Cpu technology, inc.

Software Enginer

Jul 2002 – Jul 2004 · 2 yrs

  • ★ Development of CPU based hardware acceleration system for cycle based simulation
  • ★ Netlist partitioning
  • ★ RISC based CPU computer architecture and performance evaluation
  • ★ C++, Design Patterns
CPU based hardware accelerationCycle based simulationNetlist partitioningRISC based CPU architectureC++Design Patterns+1

Synplicity

Software Enginer

Jul 1998 – Jul 2002 · 4 yrs

  • ★ Software for development for FPGA synthesis
  • ★ Software development for emulation system using FPGAs
  • ★ C, Windows
  • ★ Experience in working in small start-up environment
FPGA synthesisSoftware developmentCWindowsEDAFPGA

Atmel corporation

Software Engineer

Apr 1993 – Apr 1998 · 5 yrs

  • ★ Developed XOR based logic optimizer for ATMEL FPFAs
  • ★ Worked on software system for exploring FPGA architectures
  • ★ Worked on software used for reconfiguring FPGA systems
  • ★ Developed Flash memory controller in Verilog and implemented in FPGA
  • ★ Developed Universal Asynchronous Receiver Controller in Verilog
Logic optimizerFPGA architecturesVerilogFPGA

Semiconductor complex ltd

Software Engineer

Apr 1988 – Apr 1990 · 2 yrs

  • ★ Development of Design rule checking system for VLSI layouts
  • ★ Development of Electrical rule checker for VLSI layouts
Design rule checkingElectrical rule checker

Education

The University of Texas at Arlington

Master’s Degree — Computer Science

Jan 1991 – Jan 1993

Institute of Technology (Banaras Hindu University), Varanasi

Master of Technology (M.Tech.) — Micro Electronics

Jan 1986 – Jan 1987

Dr. Babasaheb Ambedkar Marathwada University, Aurangabad

Bachelor’s Degree — Electronics Engineering

Jan 1982 – Jan 1986

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