Dr. Namrata Gupta

Product Engineer

Raipur, Chhattisgarh, India14 yrs 8 mos experience

Key Highlights

  • Expert in Verilog and UVM methodologies.
  • Experience in TCAD tools and MEMS design.
  • Strong academic background in VLSI and Microelectronics.
Stackforce AI infers this person is a VLSI and Semiconductor Design Engineer with expertise in verification methodologies.

Contact

LinkedIn

Skills

Core Skills

VerilogUniversal Verification Methodology (uvm)

Other Skills

SystemVerilogTCAD Tools: SilvacoCadanceSpice (P-spice, TSpice)Modelsim simulatorMultiphysics COMSOL for MEMS DesignVHDL

Experience

14 yrs 8 mos
Total Experience
2 yrs 8 mos
Average Tenure
1 yr
Current Experience

Silicon patterns

Design and Verification Engineer

Jun 2025 – Present · 1 yr · Raipur, Chhattisgarh, India · On-site

VerilogUniversal Verification Methodology (UVM)SystemVerilogTCAD Tools: SilvacoCadanceSpice (P-spice, TSpice)+3

Shri shankaracharya institute of professional management & technology, raipur

Assistant Professor

Dec 2024 – May 2025 · 5 mos · Raipur, Chhattisgarh, India · On-site

Synopsys inc

2 roles

R&D Engineering, Sr Engineer at Synopsys Inc.

Promoted

Feb 2024 – Sep 2024 · 7 mos · Noida, Uttar Pradesh, India

R&D Engineer, II

Jun 2022 – Apr 2024 · 1 yr 10 mos · Noida, Uttar Pradesh, India

Nit raipur

Research Scholar

Aug 2017 – Jun 2022 · 4 yrs 10 mos · India

Bhilai institute of technology kendri, raipur

Assistant Professor

Jun 2012 – Aug 2017 · 5 yrs 2 mos · Raipur, Chhattisgarh, India

Rungta college of engineering & technology kohka-kurud bhilai.

Assistant Professor

Jun 2011 – Jun 2012 · 1 yr · Bhilai, Chhattisgarh, India

Education

National Institute of Technology Raipur

Doctor of Philosophy

Aug 2017 – Jun 2022

Indian Institute of Technology, Kharagpur

Master of Technology - MTech — Microelectronics and VLSI Design

Jan 2009 – Jan 2011

Government Engineering College Raipur

B.E. — Electronics and Telecommunication Engineering

Jan 2005 – Jan 2009

Stackforce found 100+ more professionals with Verilog & Universal Verification Methodology (uvm)

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