Punyaslok swain — Software Engineer

Greetings! Welcome to my LinkedIn profile. I'm a passionate Research and Development Engineer specializing in verification methodologies, Verilog, System Verilog, and Universal Verification Methodology (UVM). Currently, I am a part of the esteemed EDAG team at Synopsys Inc., a leading company in electronic design automation and semiconductor intellectual property. With a solid foundation in verification techniques, I bring a wealth of knowledge and expertise to my role. I thrive in challenging environments where innovation and problem-solving skills are valued, and I am always eager to contribute to cutting-edge technological advancements. During my tenure at Asiczen Technologies, where I spent 10 months, I gained invaluable experience in ASIC verification and honed my skills in Verilog and System Verilog. Collaborating with cross-functional teams, I actively contributed to the development and implementation of complex verification environments, ensuring the functionality and reliability of ASIC designs. My proficiency in Universal Verification Methodology (UVM) enables me to architect and develop reusable verification IP and verification components, enhancing the efficiency and effectiveness of the verification process. I possess a deep understanding of industry standards and best practices, allowing me to deliver high-quality verification solutions that meet stringent project requirements. Beyond my technical expertise, I am a strong communicator and thrive in collaborative environments. I value teamwork and believe in fostering a positive and inclusive work culture. I enjoy sharing knowledge and mentoring junior colleagues, empowering them to reach their full potential. Feel free to reach out to me via LinkedIn or through my contact information provided. I look forward to engaging in meaningful discussions and expanding my professional network.

Stackforce AI infers this person is a Semiconductor and EDA expert with a focus on ASIC verification.

Experience: 6 yrs 3 mos