Rajesh Bhau

Software Engineer

Noida, Uttar Pradesh, India8 yrs experience

Highly Stable

Key Highlights

8+ years in semiconductor validation.
Expert in ARM architecture and communication protocols.
Proficient in validation methodologies and automation strategies.

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in ARM architecture and debugging methodologies.

Contact

Skills

Core Skills

DebuggingSystem On A Chip (soc)Embedded SystemsValidation Engineering

Other Skills

GolangARM DS connectivityVCDTarmacNOC trace decodingEmbedded CValidation plansTest casesPythonDAP protocolLogic analyzerQtPython (Programming Language)C (Programming Language)

About

Results-driven System Validation Professional with over 8+ years of experience (including 11 months internship) in post/pre-silicon validation within the semiconductor industry. Expert in ARM Coresight debug validation and proficient in developing validation plans, validation methodologies, execution, and automation strategies. Demonstrated expertise in ARM architecture and communication protocols, including UART, SPI, and I2C, as well as programming languages C and Python.

Experience

8 yrs

Total Experience

2 yrs 4 mos

Average Tenure

1 yr

Current Experience

Renesas electronics

Senior Staff Emulation Engineer

Jun 2025 – Present · 1 yr · Noida, Uttar Pradesh, India

Intel corporation

2 roles

Emulation/Post-Si Validation Engineer

Promoted

May 2024 – Jun 2025 · 1 yr 1 mo · Bengaluru, Karnataka, India · Hybrid

System Validation Engineer

Jul 2023 – Apr 2024 · 9 mos · Bengaluru, Karnataka, India · Hybrid

1. Implemented debug tool methodology on SOC FPGA by establishing ARM DS connectivity for the hard processor system, capturing STM HWEVENTS and ETM instruction traces in VCD and Tarmac formats using Golang scripts, and enabling NOC trace decoding through custom scripting
2. Mentored both an intern and a full-time employee on this methodology.

GolangARM DS connectivityVCDTarmacNOC trace decodingDebugging+1

Nxp semiconductors

2 roles

Lead validation engineer

Apr 2022 – Jun 2023 · 1 yr 2 mos

1. Complete Validation Ownership of ARM coresight Debug Subsystem for Automotive Silicon
a. Developed comprehensive validation plans and test cases in the early stages of projects for execution in pre-silicon environments (Zebu).
b. Executed validation plans on silicon, documented silicon defects, and drove closure through successful debugging in collaboration with verification and design teams.

Embedded CValidation plansTest casesDebuggingSystem on a Chip (SoC)

Senior Validation Engineer

Jan 2020 – Apr 2022 · 2 yrs 3 mos

Managed complete validation ownership of low power timers and debug subsystems for edge processing silicon, including developing validation plans and test cases in pre-silicon environments (Zebu), executing validation on silicon, and driving defect closure in collaboration with design and verification teams.

Embedded CPythonDebuggingEmbedded Systems

Infineon technologies

Validation Engineer

Jul 2017 – Jan 2020 · 2 yrs 6 mos · Bengaluru, Karnataka, India

Assumed complete ownership of Infineon's Multicore debug solution validation, including validation plan preparation, test case development and execution on emulation and silicon, result comparison and reporting, as well as in-depth understanding of the DAP protocol and capturing results using a logic analyzer

Embedded CDAP protocolLogic analyzerValidation Engineering