Karthick chandra

DevOps Engineer

Bengaluru, Karnataka, India3 yrs 6 mos experience

Key Highlights

Expert in ASIC physical design and STA.
Experience with advanced technology nodes down to 3nm.
Proven track record in deploying new design methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC physical design and verification.

Contact

Skills

Core Skills

Physical Design VerificationStatic Timing AnalysisRtl To Gdsii

Other Skills

physical designphysical verificationsign-offPNRSignoff check tools used in industryTiming Closure

About

Enthusiastic and keen ASIC physical design/STA engineer in adapting to the new technology node and collaborating with team for self growth & team productivity.presentation skill in deploying new features in the tool to the design team with interaction and maintaining the credibility up to sign off.experience in 40,28,7,3nm technology node.good understanding to the ASIC design flow.having 1.9 years of experience in synthesis,pnr,STA,physical verification.

Experience

3 yrs 6 mos

Total Experience

1 yr 11 mos

Average Tenure

1 yr 7 mos

Current Experience

Micron technology

CONTR ASIC SR ENGINEER

Dec 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India · Hybrid

working on memory for TSMC 3,5 nm nodes phy interfaces , DRAM & NAND ,handling subsystem level physical designing, physical verification, sign-off.

physical designphysical verificationsign-offPhysical design verificationStatic Timing Analysis

Hcltech

Lead Engineer

Nov 2024 – Present · 1 yr 7 mos · Bengaluru, Karnataka, India · Hybrid

working as a lead engineer and deployed to micron as a contractor for 5,3nm projects on going.

Synopsys inc

2 roles

Application Engineer signoff primetime tool

Apr 2024 – Nov 2024 · 7 mos · Bengaluru, Karnataka, India

Working for ARM customer in deploying the primetime & primeshield tool feature.

Design technology group

Nov 2022 – Mar 2024 · 1 yr 4 mos · Bengaluru, Karnataka, India

handled two customer projects with technology node 7nm,3nm , pushing the PPA without changing the flow.Deploying the development of new methodology and QIK flows on cutting-edge technology.work on improving the existing flows and validate PPA across cores.improve product flow with automation

RTL to GDSIIPhysical design verification

Rv-vlsi vlsi and embedded systems design center

Physical Design Engineer

May 2022 – Oct 2022 · 5 mos · Bengaluru, Karnataka, India · On-site

handled lakshya project in the training phase with the macros count of 34 , 833MHz , 32K cell count,28 nm technology node,successfully completed the training with TTP 3 from design planning to signoff.

RTL to GDSIIPhysical design verification