Avijeet Somani

CTO

Bengaluru, Karnataka, India18 yrs 7 mos experience

AI ML PractitionerAI Enabled

Key Highlights

Expert in AI-driven EDA/CAD tools development.
Proven leadership in managing R&D teams.
Innovative solutions for complex chip design challenges.

Stackforce AI infers this person is a Semiconductor Architect specializing in AI-driven design automation.

Contact

Skills

Core Skills

EdaAiMl/rlR&d Management

Other Skills

Reinforcement LearningMachine LearningGoogle BigQueryProgrammingC++LinuxTeam ManagementPhysical VerificationDesign Rule Checking (DRC)Layout Versus Schematic (LVS)High Performance Computing (HPC)Parallel ProgrammingMemory ManagementPhysical DesignPyTorch

About

I am a Software Architect with extensive R&D experience, currently building AI-driven EDA/CAD tools at Google. My focus is on solving complex EDA problems and architectural challenges in chip design by combining traditional algorithmic precision with modern ML/RL techniques. With 4+ years of experience managing R&D teams, I combine hands-on technical depth and deep EDA expertise to lead complex projects from concept to completion. Core Competencies : EDA & CAD: Custom Tool Implementation, Flow Optimization, Physical Design, Physical Verification. Core Tech: C++, Python, Software Performance Optimization. Innovation: Reinforcement Learning (RL) & ML for EDA automation. Leadership: R&D Management, Project Delivery, Mentorship.

Experience

18 yrs 7 mos

Total Experience

4 yrs 3 mos

Average Tenure

1 yr 5 mos

Current Experience

Google

CAD/EDA Lead

Jan 2025 – Present · 1 yr 5 mos · Bengaluru · On-site

Driving the next generation of chip design automation by bridging the gap between EDA and AI.
AlphaChip Collaboration: Partnered with Google DeepMind to engineer timing-aware AlphaChip capabilities, utilizing Reinforcement Learning to optimize chip floorplanning and timing convergence.
Cloud-Scale CAD Infrastructure: Architecting and implementing custom CAD AI tools that leverage Google BigQuery infrastructure, enabling high-throughput analysis of EDA design data.
Innovation: Developing internal AI-driven flows that enhance the efficiency and quality of silicon implementation at Google scale.

Reinforcement LearningMachine LearningEDAAI

Cadence design systems

3 roles

Software Architect

Jul 2019 – Nov 2023 · 4 yrs 4 mos

Intelligent Chip Explorer ( tool : Cerebrus )
Created intelligent solutions using ML/RL Techniques to improve PPA(Power, Performance, Area) in the physical design space for the next-gen chips .
Physical Verification ( DFM FIll tool inside Pegasus)
Built and Managed the Pegasus India DFMFill R&D team .
Laid the foundation for the DFMFill tool and iteratively improved to productize.
Played an anchor role in making the tool scalable, feature rich and then relentlessly worked towards getting the tool qualified by multiple foundries across the globe.

ProgrammingC++EDAML/RL

Senior Principal Software Engineer

Jul 2015 – Jul 2019 · 4 yrs

Phyiscal Verification ( tool : Pegasus )
Took multiple roles within the too'sl suite, laid foundations and iteratively scaled different components of the tool to run few of the globe's largest chips .

ProgrammingC++EDA

Principal Software Engineer

Apr 2013 – Jul 2015 · 2 yrs 3 mos

Physical Verification ( tool : Pegasus)
Joined Pegasus tool when it was still an idea . Was instrumental in developing the tool's basic message passing infrastructure and then developed a plethora of core geometrical/topological processing C++ engines .

ProgrammingC++EDA