Jucemar Monteiro

Software Engineer

Sunnyvale, California, United States17 yrs 8 mos experience

Key Highlights

Ph.D. in Microelectronics with a focus on EDA algorithms.
Multi-year top-tier finisher in ICCAD and ISPD contests.
Co-author of RsynDesign, an open-source physical synthesis framework.

Stackforce AI infers this person is a highly skilled EDA professional specializing in physical optimization algorithms and high-performance computing.

Contact

Skills

Core Skills

Physical OptimizationHigh-performance ComputingEda Research

Other Skills

C++C (Programming Language)Python (Programming Language)OptimizationPlacement AlgorithmsPhysical synthesis optimizationEDAEDA physical optimizationAlgorithm OptimizationEDA High-Performance ComputingDigital Design FlowVerilogCadence toolsSynopsys toolsVHDL

About

I am a Staff R&D Software Engineer at Synopsys specializing in the research and development of high-performance physical optimization algorithms. With a Ph.D. in Microelectronics, I focus on pushing the boundaries of placement and routing to solve the industry’s most complex EDA challenges. My background is rooted in high-stakes problem solving. I am a multi-year top-tier finisher of ICCAD and ISPD international programming contests in detailed placement and routing challenges. I am also the co-author of RsynDesign, an open-source physical synthesis framework used in academic research. Core Expertise: - Physical Optimization: Advanced placement and routing algorithms. - High-Performance Computing: Large-scale C++ algorithm development and optimization. - EDA Research: Physical synthesis, digital design flows, and microelectronics.

Experience

17 yrs 8 mos

Total Experience

Average Tenure

Current Experience

Synopsys inc

4 roles

R&D Software Engineer, Senior Staff

Promoted

May 2026 – Present · 1 mo · On-site

R&D Software Engineer, Staff

Feb 2024 – May 2026 · 2 yrs 3 mos · On-site

R&D software engineer at Fusion Compiler (FC) physical synthesis. Developing AI-targeted physical optimization algorithms and enhancing Fusion Compiler synthesis flow.

C++C (Programming Language)Python (Programming Language)OptimizationPlacement AlgorithmsPhysical synthesis optimization+2

R&D Software Engineer, Sr. II

Jun 2022 – Feb 2024 · 1 yr 8 mos · On-site

I am an R&D software engineer at Design Compiler. I am developing algorithms and exploring physical synthesis flow to optimize standard cell placement, area density utilization, timing, and routability. The Quality of Results (QoR) improvement is achieved by improving existing optimization algorithms and developing new ones. Constrained optimization techniques are the foundation for implementing state-of-art optimization algorithms to improve QoR. The optimization algorithms must provide QoR improvement from different challenges and constraints in several CMOS technologies, especially in the cutting-edge ones.

OptimizationPhysical synthesis optimizationEDAC (Programming Language)C++Physical Optimization+1

R&D Software Engineer, Sr. I

May 2019 – Jun 2022 · 3 yrs 1 mo · On-site

I am an R&D software engineer at Design Compiler. I am developing algorithms and exploring physical synthesis flow to optimize standard cell placement, area density utilization, timing, and routability. The Quality of Results (QoR) improvement is achieved by improving existing optimization algorithms and developing new ones. Constrained optimization techniques are the foundation for implementing state-of-art optimization algorithms to improve QoR. The optimization algorithms must provide QoR improvement from different challenges and constraints in several CMOS technologies, especially in the cutting-edge ones.

OptimizationPhysical synthesis optimizationEDAC (Programming Language)C++Physical Optimization+1

Cadence design systems

Software Engineer Internship

Jun 2018 – Oct 2018 · 4 mos · Austin, Texas Metropolitan Area

Synopsys inc

Software Engineering Technical Internship

Oct 2017 – Apr 2018 · 6 mos · Sunnyvale

Technical Intern in the Electronic Design Automation.

University of calgary

Visiting Reseacher Student

Oct 2015 – Apr 2016 · 6 mos · Calgary, Alberta, Canada

Researching algorithms to minimize routing overflow during incremental timing-driven placement optimization. The research result was presented at DAC 2016 as a Work-In-Progress and as a regular paper ISVLSI 2016 (https://doi.org/10.1109/ISVLSI.2016.23)

Universidade federal do rio grande do sul

3 roles

Ph.D. on Microelectronics

Nov 2014 – May 2019 · 4 yrs 6 mos

Researching EDA algorithms to optimize timing and routability in the Placement.

MSc Microelectronics

Promoted

Aug 2012 – Nov 2014 · 2 yrs 3 mos

I had implemented a global quadratic placement algorithm to minimize timing violation for incremental timing-driven placement optimization. The incremental quadratic timing-driven placement algorithm only moves the critical cells and their neighbors. The remain cells were considered as fixed one.

ASIC Digital Designer

Aug 2011 – Jul 2012 · 11 mos

Universidade federal de santa catarina

Undergraduate Researcher Student (Bolsista de Iniciação Científica)

Aug 2008 – Jul 2011 · 2 yrs 11 mos · Florianópolis, Brazil

Fast adder architecture design to optimize power product delay. The adders were synthesized with commercial tools to the TSMC 45 nm library. I proposed a Hierarchical Add-One Carry-Select Adder (https://doi.org/10.1109/ICECS.2011.6122308) that was faster than Carry-Lookahead Adder.
Adders:
Carry-Ripple Adder - CRA
Carry-Select Adder - CSA
Add-One Carry-Select Adder - A1CSA
Carry-Lookahead Adder - CLA
Hierarchical Add-One Select Adder - A1CSAH