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Simon Bloyce

Associate Consultant

Andover, England, United Kingdom30 yrs experience

Key Highlights

  • Expert in timing analysis and ECO closure flows.
  • Led European technical team for Synopsys' EDA tools.
  • Accomplished communicator and team leader.
Stackforce AI infers this person is a seasoned EDA and semiconductor expert with strong leadership in technical consultancy.

Contact

Skills

Core Skills

Static Timing AnalysisEcoCustomer Support

Other Skills

Signal Integrity AnalysisEDALogic SynthesisTechnical PresentationsTechnical TrainingSignoff MethodologyTechnical Account ManagementSemiconductorsASICSoCTCLVerilogVLSIICIntegrated Circuit Design

About

I am a proficient and motivated engineer with a deep knowledge of the semiconductor, electronics and EDA industries. I am an expert in the field of timing analysis and ECO closure flows, with prior experience of RTL development and synthesis and deep knowledge of the entire rtl2gds flow. My experience has been gained across technology nodes from 0.35um to the latest finFET nodes. I deliver tool and design support, flow and methodology consultancy and technical training and guidance, directed by a deep understanding of the commercial implications of design and tooling decisions. I manage a team of world class engineers who support Synopsys’ customers throughout Europe, and globally, across our sign-off products which include STA, ECO, parasitic extraction, physical verification, ESD analysis, and constraints management. I am an accomplished communicator, leader and motivator, working with,and across, global teams, internally and externally, from individual contributor through to SVP levels.

Experience

30 yrs
Total Experience
--
Average Tenure
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Current Experience

Synopsys northern europe ltd

Senior Staff Application Consultant

Jan 2004Present · 22 yrs 5 mos · CamberleyReading, Berkshire

  • I have worked as an Application Consultant at Synopsys supporting and promoting Synopsys'​ digital implementation products since 2004.
  • My primary specialisation is static timing and signal integrity analysis (STA/SI), signoff methodology and ECO design closure flows. I have been the European technical team lead for Synopsys' market leading EDA tools in this area (PrimeTime Suite) since 2006. This position ensures that I have excellent visibility of emerging signoff technologies, good understanding of the competitive marketplace, and have regular opportunity to influence the product direction and development.
  • In addition to my signoff based activities, I am an expert in the area of logic synthesis using Synopsys Design Compiler including physical synthesis techniques, and am the technical account lead for a significant UK based IP-provider.
  • I regularly host meetings, both technical and managerial, internally and with customers. I regularly contribute to, review and deliver technical presentations and papers, and I deliver advanced technical training regularly externally and internally.
ECOStatic Timing AnalysisSignal Integrity AnalysisEDALogic SynthesisTechnical Presentations+1

Self employed

ASIC Design Consultant

May 1999May 2004 · 5 yrs

  • Various positions including Sony Semiconductors, Sony Broadcast, Sony Electronics, Hitachi Microelectronics, Atmel France, TI France

Toshiba electronics

Design Engineer

Dec 1997May 1999 · 1 yr 5 mos

C&c electronics

ASIC Designer

Apr 1997Dec 1997 · 8 mos

Gec marconi defence systems

Graduate Design Engineer

Jun 1996Apr 1997 · 10 mos

Education

Brunel University of London

Bachelor of Engineering (B.Eng.) — Microelectronics Engineering

Jan 1992Jan 1995

Dane Court Grammar School

A levels

Jan 1985Jan 1992

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