Feb 2024 – Present · 2 yrs 4 mos

• Spearheaded the SEM-GATE early RTL bring-up initiative, achieving a 40% reduction in bring-up time and 30% decrease in resource utilization, accelerating overall project timelines.
• Designed and executed Randomized UTF testing to enhance ZeBu compilation robustness, to uncover critical bugs pre-OST by experimenting with diverse UTF command permutations.
• Leading a cross-functional team of 7, driving innovation by collecting and implementing ideas across ZeBu components, fostering collaboration and measurable improvements in flow efficiency.
• Implemented incremental L0 BM setup for large design compilation, resulting in a 30% reduction in compile time and 25% savings in resource usage, optimizing throughput.
• Built ZeBu Failure Analyzer using GitHub Copilot (agentic mode) and internal LLM to streamline regression failure analysis.

Jun 2022 – Jun 2024 · 2 yrs

• Designed a Random UPF Generation framework to dynamically attach UPF constructs to RTL designs, enabling early in-house detection of power intent issues.
• Developed a Unified Automatic Regression Tracking system integrated with Jira for unit-level testcases and benchmarks, enhancing debug traceability and saving over 200 engineering hours per week across the team.
• Implemented the Scalene UPF flow to enable parallel compilation during the VCS stage, achieving a 50% reduction in front-end compile time and accelerating simulation readiness.
• Built a Randomized RTL Testing methodology, creating a stress-testing framework to proactively uncover issues linked to customer-reported Jira tickets, improving robustness .

Dec 2020 – Jun 2022 · 1 yr 6 mos

• Developed WaveBkt, an automated waveform mismatch analysis tool that reduced debug time by 50%, accelerating regression triage and improving validation efficiency.
• Engineered RTL-Stitching framework to aggregate unit-level RTLs into large-scale designs, enabling comprehensive ZeBu flow validation and enhancing scalability of test environments.
• Built a Plug-and-Play mechanism for ZeBu features, allowing dynamic enablement of compile-time and runtime options per RTL. This setup automated environment configuration and executed full ZeBu flow
• with integrated self-checking.
• Implemented lightweight UPF and developed low-power assertions to enable faster validation and early detection of power intent issues

Jan 2019 – Dec 2020 · 1 yr 11 mos

• I played a pivotal role in enhancing low-power validation processes at Synopsys Inc, achieving significant improvements in efficiency.
• Integrated UPF 2.0 support into ZeBu, enhancing validation coverage for complex designs.
• Reduced zTopBuild compile time from 1 hour to just 10 minutes through RhinoDB support.
• Achieved a 20% reduction in compile time by optimizing Power Network Modeling.

Oct 2017 – Dec 2018 · 1 yr 2 mos

• During my internship at Synopsys Inc., I focused on validating low-power runtime APIs and ensuring the stability of synthesis flows. I handled VCS synthesis regressions and validated UPF regressions using formal checks, which significantly improved power intent verification. This experience allowed me to develop strong analytical and problem-solving skills in a leading semiconductor company.