Pradeep Garg

Software Engineer

India11 yrs 11 mos experience

Key Highlights

Over 11 years of VLSI design and verification experience.
Expert in IP and SoC verification solutions.
Proven track record in delivering high-quality digital RTL designs.

Stackforce AI infers this person is a VLSI and ASIC verification specialist in the semiconductor industry.

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Skills

Core Skills

Ip VerificationFunctional VerificationUniversal Verification Methodology (uvm)Soc VerificationHardware VerificationTest PlanningRtl Design

Other Skills

PCIeSVSiliconSystem on a Chip (SoC)ProcessorsRegression TestingVLSIMicrocontrollersEmbedded SystemsDigital ElectronicsMatlabModelSimElectronicsAlgorithmsTcl-Tk

About

Seasoned VLSI specialist with over 11 years of experience in RTL Design and Verification across diversed domains. Proven track record in delivering high-quality solutions for IP and SoC verification solution and complex digital RTL designs. Core Competencies: IP, SOC, Sub-Subsystem RTL Verification SOC RTL & Gate-Level Simulation (GLS) Coverage(functional & code) and Assertion-based verification Communication & Security IP Verification ASIC & FPGA RTL Design

Experience

11 yrs 11 mos

Total Experience

Average Tenure

Current Experience

Qualcomm

Staff Engineer

Feb 2026 – Present · 4 mos · Bangalore · On-site

PCIeFunctional VerificationIP VerificationUniversal Verification Methodology (UVM)SV

Synopsys inc

2 roles

ASIC Digital Design, Staff Engineer

Dec 2024 – Jan 2026 · 1 yr 1 mo · Noida, Uttar Pradesh, India · On-site

PCIe4 PHY Controller - IP Verification.

Universal Verification Methodology (UVM)IP VerificationPCIe

ASIC Design Engr, Sr II

Oct 2022 – Dec 2024 · 2 yrs 2 mos · Noida, Uttar Pradesh, India · On-site

PCIe4 PHY Controller - IP Verification.

IP VerificationPCIeUniversal Verification Methodology (UVM)

Stmicroelectronics

3 roles

Staff Engineer

Promoted

Jun 2021 – Sep 2022 · 1 yr 3 mos

SiliconSystem on a Chip (SoC)Universal Verification Methodology (UVM)ProcessorsSOC verificationIP Verification+1

Technical Lead

Apr 2019 – Jun 2021 · 2 yrs 2 mos

SiliconTest PlanningHardware Verification

Senior Design Engineer

Feb 2018 – Apr 2019 · 1 yr 2 mos

SiliconTest PlanningHardware Verification

Hcl technologies

Lead Engineer

Feb 2017 – Feb 2018 · 1 yr · Noida Area, India

Verification lead engineer in UVM base verification projects.
Development of project specific UVM environment.
Team and task management with responsibility of 100% Functional + Code coverage.
Worked on Synopsys and Cadence AXI VIP for different projects.
Worked on Arm AMBA 4, Hyperbus and various communication protocol.

RTL DesignUniversal Verification Methodology (UVM)IP Verification

Elcom innovations private limited

Engineer - FPGA Design

Aug 2014 – Jan 2017 · 2 yrs 5 mos · Noida Area, India

Design RTL for Telecom Base system.
Create SystemVerilog and TCL base verification environment for the same.
Synthesis, timing closer with area and power management for Altera FPGA(Cyclone Series).

Test PlanningHardware Verification