Shivam Tyagi

DevOps Engineer

Agra, Uttar Pradesh, India7 yrs 4 mos experience
Highly Stable

Key Highlights

  • Expert in CPU physical design with extensive experience.
  • Led successful full chip PnR projects on advanced nodes.
  • Strong scripting skills in Python, Perl, and TCL.
Stackforce AI infers this person is a semiconductor design expert with a focus on physical design and project management.

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Skills

Core Skills

Cpu Physical DesignRtl To GdsFull Chip PnrProject Management

Other Skills

staCtsPNRLogic SynthesisRoutingSystem on a Chip (SoC)Flip ChipFloorplanningClock Tree SynthesisClock DistributionMulti voltageLow-power DesignLow Power SystemsMulti domainSignoff

About

Experienced physical design (full chip Pnr, multi voltage, multi domain flow) & AnalogLayout Engineer (worked on PLL, Rx, TX ) with a demonstrated history of working in the semiconductors industry. Skilled in Virtuoso, Custom Compiler, ICC2, Fusion compiler, Calibre, ICV, Voltus Verification: Design Rule Checking (DRC), parasitic extraction , PERC P2P, PERC CNOD, and Layout Versus Schematic (LVS), EM & IR Scripting skills in Python, Perl & TCL Automation, Technology Node: 3nm, TSMC 28nm, and GF 22Nm GF 14nm & Intel. Have Hand on Experience in full chip Tapeout (netlist to gds) Strong operations professional graduated from S.R.M.S College of Engineering and technology.

Experience

7 yrs 4 mos
Total Experience
3 yrs
Average Tenure
1 yr 2 mos
Current Experience

Qualcomm

CPU physical design Lead Engineer

Apr 2025Present · 1 yr 2 mos · On-site

  • Working on performance core CPU physical design implementation. RTL2GDS
staCtsCPU physical designRTL to GDS

Synopsys inc

Staff Physical design Engineer

Apr 2022Apr 2025 · 3 yrs · Noida, Uttar Pradesh, India · On-site

  • Led Full chip PnR projects on lower nodes like N2, N5, N3E, 7FF, 12FFC from RTL to GDS, ensuring efficient chip designs.
  • Managed IO ring planning, Multi row IO ring, Floorplanning, Power Planning, CTS & STA, handling PV cleanup for DRC, LVS, PERC, EM&IR, ESDLUP, Antenna.
  • Successfully met project deadlines at Synopsys Inc showcasing strong project management skills.
PNRstaFull chip PnRProject management

Soctronics

Engineer II

Jan 2019Mar 2022 · 3 yrs 2 mos · Greater Hyderabad Area

  • Worked on Pnr and Pv in 22FDSOI, TSMC 28nm and 14LPP

Veda iit

Engineer trainee

Jun 2018Jan 2019 · 7 mos · Hyderabad, Telangana, India

  • i am working as physical design engineer trainee

Education

Shri Ram Murti Smarak (SRMS) Institutions

b.tech — Electrical and Electronics Engineering

Jan 2014Jan 2018

kids corner happy senior sec. school

Jan 2007Jan 2013

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