Kasi Kishore Ravuri — Software Engineer
Experienced in STA, Timing Constraint development and validation across RTL and Netlist stages, with strong understanding and exposure to VLSI front-end and back-end flows.
Stackforce AI infers this person is a Semiconductor expert with a focus on static timing analysis and VLSI design.
Location: San Jose, California, United States
Experience: 2 yrs 2 mos
Skills
- Static Timing Analysis
- Timing Constraints
Career Highlights
- Expert in Static Timing Analysis and Timing Constraints.
- Proficient in VLSI front-end and back-end flows.
- Strong experience with industry-standard tools like Tempus and PrimeTime.
Work Experience
Cisco
ASIC Engineer (3 mos)
Cadence
Lead Application Engineer (3 mos)
Synopsys Inc
Sr Engineer (1 yr 11 mos)
Applications Engineering Intern (7 mos)
Education
Masters at Arizona State University
Bachelor of Technology - BTech at R.V.R. & J.C. College of Engineering