Guru Kiran Pammi

Software Engineer

Bengaluru, Karnataka, India18 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

8 years of VLSI design experience
Expert in timing analysis and digital IP integration
Proficient in multiple programming languages and tools

Stackforce AI infers this person is a VLSI Design Engineer with expertise in semiconductor design and software engineering.

Contact

Skills

Core Skills

VlsiVery-large-scale Integration (vlsi)

Other Skills

SynthesisAPRTiming AnalysisRTLGDSSynopsys DCICCPrimeTimeSQLC#.NetMOSS 2007PerlSoCXilinxC

About

VLSI Design Engineer with 8 years of experience in areas including Synthesis, Place And Route, Static Timing Analysis on industry leading process nodes and 2 years of experience in software design. Responsible for design and implementation of high frequency, multi-voltage Digital IP blocks. Job role includes integration and timing convergence of mixed-signal IP blocks across multiple PVTs.

Experience

18 yrs 6 mos

Total Experience

4 yrs 7 mos

Average Tenure

7 yrs

Current Experience

Cadence design systems

2 roles

Senior Principal Application Engineer

Jul 2022 – Present · 3 yrs 11 mos

Principal Application Engineer

Jun 2019 – Present · 7 yrs

Samsung electronics

Senior Staff Engineer

Feb 2018 – Jun 2019 · 1 yr 4 mos · Bengaluru, Karnataka, India

Intel technology india pvt. ltd.

Senior Component Design Engineer

Dec 2009 – Feb 2018 · 8 yrs 2 mos · Bengaluru, Karnataka, India

Involved in the RTL to GDS delivery of multiple blocks. Responsibilities included synthesis and APR of IPs in various projects using Synopsys DC and ICC. Post placement and routing, clean up of various LV issues like DRC, RV and metal fills are done in addition to clean ups related to routing and cell congestion. During the course of execution, multiple interactions with RTL team were needed in order to handle multiple issues related to timing and voltage domains.
After the APR is done, timing was run in PrimeTime at various PVT conditions and ECOs were implemented to address the timing issues.
Also involved in the back end design of few blocks in processor design. RTL is taken as one of the inputs. Various constraints related to timing, power, area and noise are specified. The design process involves completing the work meeting the given specifications.

SynthesisAPRTiming AnalysisRTLGDSSynopsys DC+4