Vishruth Belagavi

Software Engineer

Hyderabad, Telangana, India1 yr 10 mos experience

Key Highlights

Expert in analog mixed-signal design and verification.
Developed advanced PLL models enhancing simulation accuracy.
Proven track record in training clients on EDA tools.

Stackforce AI infers this person is a specialist in EDA with a focus on analog mixed-signal design.

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Skills

Core Skills

AmsVerificationAnalog Circuit Design

Other Skills

Cadence VirtuosoUniversal Verification Methodology (UVM)Verilog-AMSAnalog SimulationsAnalytical SkillsProduct PromotionMaterial CharacterizationTransistorsDVDDR SDRAMDesign ReviewOptimizationDigital IC DesignDesign FlowDigital Designs

About

As a Design Engineer II at Cadence Design Systems, I've honed my expertise in verification and analog mixed-signal (AMS) design since obtaining my Master of Engineering in VLSI from Manipal School of Information Sciences. My journey began with an enriching internship, where I developed Phase-Locked Loop (PLL) models and training materials, equipping clients with the tools for success in complex simulations. The skills I've cultivated are further supported by multiple Cadence certifications, enabling me to contribute effectively to our team's efforts. We've achieved significant milestones in advancing the functionality of the Virtuoso ADE Suite and Spectre AMS Designer, illustrating my dedication to driving technological progress and delivering excellence in every project we undertake.

Experience

1 yr 10 mos

Total Experience

1 yr 10 mos

Average Tenure

1 yr 10 mos

Current Experience

Cadence design systems

2 roles

Design Engineer II

Aug 2024 – Present · 1 yr 10 mos

Working on Analog mixed-signal (AMS) modeling , Verification, Regressions and netlisting for high-speed SerDes and USB interfaces using Cadence tools

AMSCadence VirtuosoVerification

Intern

Aug 2023 – Jul 2024 · 11 mos

Analog/ AMS Design Applications Intern.
Developed Phase-Locked Loop (PLL) models using Verilog-AMS within the Cadence Virtuoso ADE suite, Using advanced simulation capabilities for accurate performance analysis. Implemented Verilog-A models to simulate PLL behavior, ensuring compliance with design specifications and performance requirements.
Developed training material for customer training on EDA tools- Virtuoso ADE Suite, Spectre Analog Solver, Xcelium Logic Simulator, Spectre AMS Designer.
Responsibilities included training customers on setting up the Mixed-signal Simulation Environment, Analog Simulations.
Simlulated labs on Block level designs, documented the steps, prepared course materials and lab documents on Mixed-signal modelling with Verilog-A, Verilog-AMS and SystemVerilog RNM, Verilog-AMS wreal.

Universal Verification Methodology (UVM)Cadence VirtuosoAnalog Circuit DesignVerification