Rahul Agarwal

DevOps Engineer

Bengaluru, Karnataka, India10 yrs 1 mo experience

Key Highlights

Expert in Physical Design and Timing Closure.
Experience with multiple technology nodes from 16nm to 3nm.
Involved in high-frequency designs up to 3.2GHz.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and ASIC methodologies.

Contact

Skills

Other Skills

VerilogLinuxPublic SpeakingPerlApplication-Specific Integrated Circuits (ASIC)ElectronicsPythonAdobe PhotoshopVLSIVery-Large-Scale Integration (VLSI)TCLStatic Timing AnalysisRTL DesignPhysical DesignRTL Verification

About

• Good understanding in all aspects of Physical Design involving synthesis, PnR and timing closure • Involved in multiple tape outs of design varying from 795Mhz to 3.2GHz frequency • Worked on SubFC level PnR and timing closure containing 2 blocks • Experience in Low Power Designs with UPF 2.0 • Worked on multiple technologies varying from 16nm to 3nm

Experience

10 yrs 1 mo

Total Experience

Average Tenure

Current Experience

Ibm

Advisory R&D Engineer

Aug 2025 – Present · 10 mos · Bengaluru · Hybrid

Synopsys inc

2 roles

R&D Engineering, Staff Engineer

Feb 2024 – Aug 2025 · 1 yr 6 mos · Bengaluru, Karnataka, India · Hybrid

Part of the ASG/Ecosystem RnD India BU. Key responsibilities/activities include
Improving the Synopsys' QiK implementation flows for wider adaptability across CPU RISC-V based ecosystems
Technology-workflow integration for improved PPA across said ecosystems
Specialised customer support model for quicker TAT on some lead-partner engagements

R&D Engineer, Sr II

Jul 2023 – Feb 2024 · 7 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

SoC Design Engineer

Oct 2018 – Jun 2023 · 4 yrs 8 mos · Bengaluru Area, India · Hybrid

Part of SDG/NEXG/XEG India BU, I was :
Responsible for RTL to GDSII implementation of IPs in Flagship server processors on the latest and most advanced multiple technology nodes

Insilico

Physical Design Engineer

Aug 2017 – Jul 2018 · 11 mos · Bengaluru Area, India

Worked at client, Microsemi (Microchip) on various partitions, subsystem having responsibility of delivering final gdsii which accounted of PnR, STA, Power and PV closure.
Also, Full chip level power, LVS, DRC Cleaning.

Incise infotech private limited

Physical Design Engineer (Trainee)

Aug 2016 – Apr 2017 · 8 mos

Netlist to GDS Implementation of the design which included floor planning, Power Mesh generation, PNR, CTS, Fixing Violations (Setup and Hold time), Physical Verification, Crosstalk etc. using CADENCE SOC ENCOUNTER tool.