Siva Naga Jyothi G. — Software Engineer
Expert in Physical Design and synthesis, Floor Planning,Placement,clock tree synthesis, routing,Static Timing Analysis, PV Analysis, LEC,IR Analysis and worked for TSMC 3nm,4nm ,5nm, 7nm, 14nm, 28nm and Intel 10nm Projects.
Stackforce AI infers this person is a Physical Design Engineer specializing in advanced semiconductor technologies.
Location: Hyderabad, Telangana, India
Experience: 8 yrs 11 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in Physical Design for advanced nodes.
- Proficient in Static Timing Analysis and Physical Verification.
- Experience with TSMC and Intel projects across multiple technology nodes.
Work Experience
Synopsys Inc
ASIC Physical Design Engineer staff engineer (1 yr 11 mos)
Senior Physical Design Engineer (1 yr 8 mos)
eInfochips (An Arrow Company)
Senior Physical Design Engineer (1 yr 9 mos)
Cerium Systems
Senior Physical Design Engineer (1 yr 7 mos)
Intel Corporation
Senior Physical Design Engineer (1 yr 7 mos)
ChipSil Technologies Pvt Ltd
Physical Design Engineer (1 yr)
Vaaluka Solutions
Physical Design Engineer (2 yrs 8 mos)
Education
Master of Technology - MTech at BITS Pilani Work Integrated Learning Programmes
Bachelor of Technology - BTech at Velagapudi Ramakrishna Siddhartha Engineering College