S

Subhadeep Bandopadhyay

Software Engineer

Kolkata, West Bengal, India2 yrs 9 mos experience

Key Highlights

  • Senior Validation Engineer with expertise in static timing analysis.
  • MTech in Embedded Systems from a prestigious institute.
  • Hands-on experience with Tcl-Tk and digital IC design.
Stackforce AI infers this person is a skilled Validation Engineer in the semiconductor industry with a focus on digital design.

Contact

Skills

Core Skills

Static Timing Analysis

Other Skills

Tcl-TkTime ConstraintsClock Tree SynthesisTiming ClosureLogic SynthesisPNRPrime TimeCMOSLinuxVerilogSystem Design using Verilog HDLC (Programming Language)Xilinx VivadoDigital IC DesignARM Cortex-M

Experience

2 yrs 9 mos
Total Experience
--
Average Tenure
--
Current Experience

Synopsys inc

3 roles

Senior Validation Engineer

Promoted

Feb 2024Present · 2 yrs 4 mos · Bengaluru, Karnataka, India

Application Engineer ll

Sep 2023Feb 2024 · 5 mos · Bengaluru, Karnataka, India

Technical Intern

Aug 2022Sep 2023 · 1 yr 1 mo · Bengaluru, Karnataka, India

Static Timing AnalysisTcl-Tk

Education

National Institute of Technology Jamshedpur

Master of Technology - MTech — Embedded Systems Engineering

Sep 2021Jan 2023

Kalyani Government Engineering College

Bachelor of Technology - BTech — Electronics and Communications Engineering

Aug 2015Jun 2019

Bankura Zilla School

XII

Mar 2013Apr 2014

Bankura Zilla School

X

Jan 2011Jan 2012

Stackforce found 100+ more professionals with Static Timing Analysis

Explore similar profiles based on matching skills and experience