Ganesh Lande — Software Engineer

Senior FPGA Prototyping & SoC Partitioning Engineer with hands-on expertise in mapping large-scale, multi-million LUT SoC designs onto multi-FPGA prototype platforms for pre-silicon verification. Specialized in congestion-aware netlist partitioning, place-and-route optimization, and timing closure across complex multi-clock prototype builds. Architected and trained an Agentic Al-driven Partitioning Strategy Agent by contributing deep hardware domain knowledge, FPGA prototyping concepts, and SoC architecture expertise to drive its development - then systematically trained the agent by defining partitioning rules and skillsets covering LUT utilization thresholds, connectivity affinity, inter-FPGA hop minimization, route-through analysis, cluster isolation policies, and multi-rule conflict resolution enabling fully autonomous, scalable FPGA placement decisions on large-scale SoC prototypes Proven track record of driving measurable prototype improvements: ~54% reduction in FPGA footprint,>55% cut in inter-FPGA signal count, and 66-90% inter-cluster latency reduction - through intelligent block placement, critical-path- aware co-location, and Al-assisted XDC constraint generation. Passionate about pushing the boundaries of agentic Al learning, EDA automation, and congestion-aware prototyping to accelerate next-generation silicon verification at scale

Stackforce AI infers this person is a specialist in FPGA prototyping and SoC design within the semiconductor industry.

Location: Bangalore Urban, Karnataka, India

Experience: 4 yrs 11 mos