Daniel Giftson E

Software Engineer

Chennai, Tamil Nadu, India1 yr 7 mos experience

Key Highlights

Specialized in RTL design and functional verification.
Presented at VLSID Conference 2023 with top 12 proposal.
Certified Microsoft Technology Associate for Security Fundamentals.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on Memory Controller and Verification.

Contact

Skills

Core Skills

Rtl DesignFunctional VerificationMemory ControllersUniversal Verification Methodology (uvm)

Other Skills

TeamworkOwnershipLPDDRPerformance OptimizationUVMVerification IPAnalog Test ChipDFITest PlanningSolidityVulnerability AssessmentSystem HackingFirmwareSilicon ValidationGate Level Simulation

About

Design and Verification Engineer with 1.5+ years full-time +1 year internship experience at Ceremorphic Technologies, specializing in RTL design and functional verification of the in-house LPDDR5/5X Memory Controller and LPDDR6 PHY Digital Block. Skilled in UVM, RTL Design, and Linting . Proficient in AXI, LPDDR, and DFI protocols. In my undergrad time at IITGN, led and worked on projects and paper publications on In-memory computing, ML Hardware Accelerator, and Processor designs. Notably, implemented and presented our proposal of "Fast and Efficient ML Hardware Accelerator Designs for SoCs with integrated FPGA" on the Microchip Technology's RISC-V based PolarFire SoC Icicle Kit at the VLSID Conference 2023 as part of the top 12 proposals shortlisted in the VLSID Design Contest 2023. Moreover, got certified as a Microsoft Technology Associate for Security Fundamentals by Microsoft, Passionate on learning and getting hands-on experience onto the new and emerging technologies in the VLSI industry.

Experience

1 yr 7 mos

Total Experience

Average Tenure

Current Experience

Ceremorphic, inc.

2 roles

ASIC Design and Verification Engineer

Jun 2024 – Jan 2026 · 1 yr 7 mos · Hyderabad, Telangana, India

Enhanced the existing LPDDR5/5X MC by feature additons, performance optimizations, bug-fixes and linting.
Worked on bringing up a stable UVM testbench and developed testcases for the block-level verification of the LPDDR5/5X memory controller.
Carried out functional and performance verification on LPDDR5/5X Memory Subsystem containing MC and Physical Layer (PHY) both as DUT alongside LPDDR5/5X Memory VIP.
Contributed to the functional verification of the LPDDR6 PHY Digital Block (PDB) as part of the Analog test chip, which was recently successfully taped out at the 16nm technology node.
Performed gate-level simulations using pre- and post-layout netlists and SDFs for both LPDDR6 PHY and full chip to ensure timing and functional correctness after synthesis and layout.
Currently working on architecture/micro-architecture/design/verification of LPDDR6 Subsystem for the upcoming 16nm ML chip tapeout.

TeamworkOwnershipRTL DesignFunctional Verification

Digital Design Intern

May 2023 – May 2024 · 1 yr · Hyderabad, Telangana, India

Worked on the functional verification of our custom LPDDR5/5X Memory Controller.
Defined testplan and carried out module-level verification for the memory controller module interacting with DFI Status Interface.
Defined block-level and system-level testplans for memory controller verification.
Worked on evaluation of Synopsys DFI and LPDDR VIPs as well as memory subsystem VIP integration with memory controller as DUT and AXI, DFI and LPDDR VIP as agents in the tb environment.
Developed linux shell and python scripts for facilitating testcase regression and to extract JEDEC timing parameters and configurations from the spec. for the design team to architect and design the memory controller timing block.

LPDDRDFIFunctional VerificationMemory Controllers