Kotapati Dheeraj — Software Engineer
I’m a Physical Design Engineer with 6+ years of experience in RTL-to-GDSII implementation, specializing in timing closure, PPA optimization, and advanced node challenges at lower technologies. I’ve worked extensively on FC,Innovus,ICC2 and Tempus, handling Synthesis, floorplanning, CTS, routing, EMIR, and physical verification. My focus is on delivering low-power, high-performance designs through close collaboration with cross-functional teams.
Stackforce AI infers this person is a Physical Design Engineer specializing in VLSI and semiconductor industries.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 5 mos
Career Highlights
- 6+ years in RTL-to-GDSII implementation.
- Expert in timing closure and PPA optimization.
- Proficient with Cadence tools for physical design.
Work Experience
Broadcom
Senior Physical Design Engineer (8 mos)
Intel Corporation
Soc Design Engineer (5 yrs 1 mo)
Physical Design Engineer (6 mos)
LakshSemi
Physical Design Engineer (8 mos)
Education
BTech - Bachelor of Technology at SRM IST Chennai
Intermediate at Sri Chaitanya College of Education
10th class at Keshava Reddy Concept school Ananthapuram