Kotapati Dheeraj

Software Engineer

Bengaluru, Karnataka, India6 yrs 5 mos experience
Highly Stable

Key Highlights

  • 6+ years in RTL-to-GDSII implementation.
  • Expert in timing closure and PPA optimization.
  • Proficient with Cadence tools for physical design.
Stackforce AI infers this person is a Physical Design Engineer specializing in VLSI and semiconductor industries.

Contact

Skills

Other Skills

CadencevlsiP&RFloorplanningRoutingctsICCStatic Timing AnalysisPhysical DesignPhysical VerificationDFTRTL CodingCadence EncounterLow-power DesignVclp

About

I’m a Physical Design Engineer with 6+ years of experience in RTL-to-GDSII implementation, specializing in timing closure, PPA optimization, and advanced node challenges at lower technologies. I’ve worked extensively on FC,Innovus,ICC2 and Tempus, handling Synthesis, floorplanning, CTS, routing, EMIR, and physical verification. My focus is on delivering low-power, high-performance designs through close collaboration with cross-functional teams.

Experience

6 yrs 5 mos
Total Experience
3 yrs 1 mo
Average Tenure
8 mos
Current Experience

Broadcom

Senior Physical Design Engineer

Oct 2025Present · 8 mos · Singapore

  • Consultant

Intel corporation

2 roles

Soc Design Engineer

Promoted

Sep 2020Oct 2025 · 5 yrs 1 mo · Bengaluru, Karnataka, India

Physical Design Engineer

Jan 2020Jul 2020 · 6 mos · Bengaluru Area, India

Lakshsemi

Physical Design Engineer

Dec 2019Aug 2020 · 8 mos · Bengaluru Area, India

Education

SRM IST Chennai

BTech - Bachelor of Technology — Electrical and Electronics Engineering

Jan 2014Jan 2018

Sri Chaitanya College of Education

Intermediate — MPC

Jan 2012Jan 2014

Keshava Reddy Concept school Ananthapuram

10th class

Jan 2011Jan 2012

Stackforce found 100+ more professionals with Cadence & vlsi

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