Kiranjyoti Pujari — Software Engineer
3+ years of experience as a Sr. R&D Engineer at Synopsys, focused on Design Verification - UVM, SystemVerilog, testbench debug, and customer verification support on production designs. Hands-on with AMBA protocols (APB) and bus-centric verification environments, along with constrained-random verification, SVA assertions, and coverage-driven closure. Proficient in Python scripting for automation,log/debug analysis and flow efficiency.Continuously growing in advanced DV and protocol-based testbench development. Verification is the domain I work in and invest in every day.
Stackforce AI infers this person is a Design Verification Engineer with expertise in semiconductor and digital design industries.
Location: Bhubaneswar, Odisha, India
Experience: 3 yrs 8 mos
Skills
- Design Verification
- Uvm
- Digital Design
- Verification
Career Highlights
- 3+ years in Design Verification at Synopsys
- Expertise in UVM and SystemVerilog
- Proficient in Python for automation and debugging
Work Experience
Synopsys Inc
Senior Research And Development Engineer (1 yr 4 mos)
Research And Development Engineer (1 yr 7 mos)
Asiczen Technologies
Digital Design Engineer (9 mos)
Education
Bachelor of Engineering - BE at Silicon Institute of Technology (SIT), Sambalpur
Higher Secondary education at Vikash The Concept school
Secondary education at Aditya residential school