DURVESULA REVANTH

Software Engineer

Bengaluru, Karnataka, India4 yrs 4 mos experience
Highly Stable

Key Highlights

  • Experienced in Verilog and SystemVerilog for design verification.
  • Strong foundation in engineering principles from a reputable institution.
  • Proficient in multiple programming languages and tools.
Stackforce AI infers this person is a Verification Engineer with expertise in hardware design and verification methodologies.

Contact

Skills

Core Skills

VerilogSystemverilog

Other Skills

Universal Verification Methodology (UVM)ResearchMicrosoft WordPublic SpeakingMicrosoft OfficeAdobe PhotoshopMatlabC (Programming Language)C++Team BuildingEnglish

Experience

4 yrs 4 mos
Total Experience
4 yrs 4 mos
Average Tenure
4 yrs 4 mos
Current Experience

Cadence design systems

2 roles

Solutions Engineer

Feb 2022Present · 4 yrs 4 mos

VerilogSystemVerilogUniversal Verification Methodology (UVM)

Intern Solutions

Apr 2021Jan 2022 · 9 mos

Maven silicon

Trainee

Nov 2020Apr 2021 · 5 mos · Bengaluru, Karnataka, India

Nautical wings

Technical Project Lead

May 2017Mar 2019 · 1 yr 10 mos · Bengaluru Area, India

Education

Sir M Visvesvaraya Institute of Technology, BANGALORE

Bachelor of Engineering - BE — ECE

Jan 2016Jan 2020

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DURVESULA REVANTH - Software Engineer | Stackforce