Shubham Patil — Software Engineer
Design Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Strong engineering professional with a BE - Bachelor of Engineering focused in Electrical and Electronics Engineering from AISSMS College of Engineering, Pune.
Stackforce AI infers this person is a Semiconductor Design Verification Engineer with expertise in SOC and UVM methodologies.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 11 mos
Skills
- Soc Design
- Universal Verification Methodology (uvm)
- System On A Chip (soc)
Career Highlights
- Experienced in SOC Design and Verification.
- Proficient in UVM and SystemVerilog methodologies.
- Strong background in semiconductors industry.
Work Experience
Synopsys Inc
Staff Engineer (1 yr 6 mos)
Senior Engineer (1 yr)
SOC Engineer, II (1 yr)
Cerium Systems
Design Verification Engineer (3 yrs 5 mos)
Education
Bachelor of Engineering - BE at AISSMS College of Engineering
