Charan Kruthik

Intern

Austin, Texas, United States3 yrs experience

Highly Stable

Key Highlights

3+ years of experience in ASIC design.
Led significant USB IP enhancements and resolved complex design issues.
Passionate about learning and applying new technologies.

Stackforce AI infers this person is a Semiconductor ASIC Design Engineer with expertise in RTL and microarchitecture.

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Skills

Core Skills

Asic Design

Other Skills

Machine LearningRTL DesignApplication-Specific Integrated Circuits (ASIC)MicroarchitectureCPU microarchitectureVerilog/SystemVerilogC++Microprocessor architectureCDC/RDC/LintSpyglass/VC SpyglassHardware ArchitectureSynopsys toolsMIPI UniProHigh-speed Digital DesignMPHY

About

✨ Passionate Student pursuing MS in Computer Engineering at NCSU 📖 🧐Looking for opportunities in ASIC Design, CPU/GPU design and RTL design. 💻3+ years of hands-on experience as Senior ASIC Design Engineer at Synopsys - worked on cutting-edge complex UniPro 3.0 and 2.0 controller designs and USB 3x and USB 2x controller designs! 💻Technical Specifications known: MIPI UniPro 3.0, UniPro 2.0, USB2.0, eUSB2, LPM, AMBA, UTMI, ULPI, basics of USB3.2 and xHCI 🙏Always in pursuit of learning and application of the little learnt! 🙏

Experience

3 yrs

Total Experience

3 yrs

Average Tenure

Current Experience

Qualcomm

NPU RTL Intern

May 2026 – Present · 1 mo · Austin, TX · On-site

ASIC DesignMachine Learning

Synopsys inc

3 roles

Senior ASIC Digital Design Engineer

Feb 2025 – Jul 2025 · 5 mos

MIPI UniPro 3.0 IP Development
✅ Owned and delivered RTL design modules for 3 major MIPI UniPro 3.0 controller releases.
✅ Drove end-to-end design cycle: Design Architecture → Functional Specification → RTL implementation under aggressive timelines.
✅ Ensured clean static RTL checks - Lint, CDC, and RDC, and achieved clean Synthesis with Timing closure.

RTL DesignApplication-Specific Integrated Circuits (ASIC)ASIC Design

ASIC Digital Design Engineer

Jun 2022 – Feb 2025 · 2 yrs 8 mos

USB IP Development
✅ Contributed to 5 major USB IP controller releases (v2, v3x, eUSBx)
✅ Led significant product enhancement: from architecture development to RTL implementation.
✅ Strong understanding of USB controller micro-architecture: functionality of various modules involved in control path and data path, from application interface to the USB PHY interface.
✅ Resolved 75+ CDC violations across multiple clock domains in the design by employing best synchronization strategies based on signal behavior and use case, adding relevant tool constraints. Owned the VC Spyglass tool flow across all design goals.
✅ Debugged 100+ simulation failures by analyzing testcase scenarios, tracing FSM states and signal behavior across protocol layers, and resolving root-cause RTL bugs.

Application-Specific Integrated Circuits (ASIC)MicroarchitectureASIC Design