V

Vinayaraj PG

Design Manager

Kasaragod, Kerala, India15 yrs 5 mos experience

Key Highlights

  • Nearly ten years of experience in VLSI design.
  • Expert in Standard Cell Library development and verification.
  • Worked on advanced technologies from 40nm to 3nm nodes.
Stackforce AI infers this person is a VLSI design expert specializing in advanced semiconductor technologies.

Contact

LinkedIn

Skills

Core Skills

VlsiStandard Cell Layout Design

Other Skills

Cadence VirtuosoVerificationCustom IC layout designStandardcell/IO layout design14nm TechnologyIC mask layout designStandardCell LayoutPhysical VerificationEDA ToolsDebuggingFPGACVerilogC++Embedded Systems

About

I am a custom Layout Design Engineer nearly ten years of experience. I am specifically into Standard Cell Library development and it's verification. I have worked on technologies ranging from 40nm to 3nm nodes.

Experience

15 yrs 5 mos
Total Experience
--
Average Tenure
--
Current Experience

Synopsys inc

Layout Design Manager

Jan 2020 – Present · 6 yrs 5 mos · Bengaluru Area, India

  • Standard cell layout design engineer Sr.
Standard cell layout designVLSICadence Virtuoso

Arm (contract through aricent)

Standard Cell layout Design Engineer

Sep 2015 – Jan 2020 · 4 yrs 4 mos · Bengaluru Area, India

  • Standard Cell layout design and verification
Standard Cell layout designVerificationVLSI

Smartplay technologies

Senior Engineer

Jun 2015 – Jan 2020 · 4 yrs 7 mos · Bengaluru Area, India

  • Custom IC layout Designer
Custom IC layout designVLSI

Intel mobile communication ( contract through nest)

Layout Design Engineer

Jul 2013 – Jun 2015 · 1 yr 11 mos · Bengaluru Area, India

  • Standardcell/IO layout design.
  • 14nm Technlogy (Finfet)
Standardcell/IO layout design14nm TechnologyStandard Cell layout design

Quest global (erstwhile nest software)

VLSI Design Engineer

Jan 2011 – Jun 2015 · 4 yrs 5 mos · Bengaluru Area, India

  • IC mask layout design engineer
IC mask layout designVLSI

Nest technologies

Layout Design Engineer

Jan 2011 – Jun 2013 · 2 yrs 5 mos · Trivandrum

  • Strong StandardCell Layout skills
  • Layout training in Analog and IO layout.
  • Physical Verification (DRC,LVS,DIVA,ERC,DFM,ANTENNA) Using Industry Standard .
  • EDA Tools.
  • Experience in 28nm,40nm,55nm,65nm technlogies.
  • Experience in cadence virtuoso L and XL.
StandardCell LayoutPhysical VerificationEDA ToolsStandard Cell layout design

Education

CUSAT college of engineering Trikaripur

Engineer’s Degree

Jan 2006 – Jan 2010

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