Bharat Suthar

Product Engineer

Bengaluru, Karnataka, India2 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in advanced technology nodes like 2nm and 3nm.
Proficient in standard cell layout design and development.
Experience with leading foundries including TSMC and Samsung.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in advanced VLSI technologies.

Contact

Skills

Core Skills

Layout DesignStandard Cell Development

Other Skills

Layout Versus Schematic (LVS)Design Rule Checking (DRC)Cadence VirtuosoCMOSDesignControl SystemDigital logic designDigital vlsi designMicrowindSemiconductor DeviceStatic Timing AnalysisVlsi physical designXilinx ISEVerilog HDLXilinx Vivado

About

Worked on advanced technology nodes (2nm/3nm/4nm) for leading foundries including Samsung, TSMC, GF, Rapidus, and Intel as a Standard Cell Layout Design Engineer, covering combinational cells, sequential elements, and multi-bit flip-flops.

Experience

2 yrs 7 mos

Total Experience

2 yrs 7 mos

Average Tenure

Current Experience

Synopsys inc

4 roles

Standard cell circuit design, Sr Engineer

Promoted

Jul 2024 – Jan 2026 · 1 yr 6 mos

Worked in circuit development, extraction, QoR.
Experience in GF, N4C, Rapidus, Intel for circuit library development.

Layout Versus Schematic (LVS)Design Rule Checking (DRC)Cadence VirtuosoCMOSDesignControl System+9

Layout Design, Sr Engineer

Feb 2024 – Jul 2024 · 5 mos

A&MS Layout Design Engr II

Jun 2023 – Feb 2024 · 8 mos

Working as A&MS Layout Design Engineer.
Developed standard cells from scratch combinational & sequential (FF, latch) cells on latest technology nodes (2nm, 3nm & 4nm) using Synopsys Custom compiler (CC), this technology includes TSMC as well as Samsung also.
Experience in ICC2 pin access abutment.
Developed ECO cells, POK cells, Level shifters, DCAP cells, Filler cells, clock gating cells, PGAT cells.
Worked in big drives in the latest technology node.
Worked in MBFF for latest technology node.
Developed HASH & DONUT design for validation of ENDCAP cells in SS4 & SS8.
Worked for optimisation of area in the standard cells & Optimisation of higher metal in standard cells like M2 & M3.
Fixed EM for higher drive buffer and inverters (like 128, 164 etc)
Worked in SS4 for DFM fix activity.
Worked in EM fix activity in SS8 in diff lib
Scratch development of tap cells, inner corner cells, fill cells, endcap cells in SS8 and validated through Donut & Hash design for Different VTs Layers.
Scratch development of level shifters in SS8