Bhargav S — Software Engineer

Core Expertise: With a robust background in ASIC/FPGA Architecture Design, RTL Coding, Simulation, and adeptness in Low Power Methodologies, Lint CDC & RDC analysis, Synthesis, Static Timing Analysis, Formal Verification, and Documentation, I am at the forefront of technological innovation and precision engineering. Knowledge of ASIC Products: My expertise is showcased through my contributions to Nvidia's premier GPU and CPU product lines, focusing on the design and verification of cutting-edge low-power features. Further, my work on Synopsys' USB 3.2/4 IP design and verification has honed my skills in Link and protocol adapter layers, enriched by exposure to the xHCI specification, and AXI and AHB protocols. AI Expertise: Proficient in AI/ML, I specialize in automating ASIC Front-End tasks, developing AI models that revolutionize design and verification processes. This includes Specification parsing, generating test lists tailored to design changes, and enhancing bug triaging and debug assistance. Tool Exposure: I possess hands-on experience with EDA tools including Spyglass/VC Spyglass, VC Formal (FPV, SEQ, AEP & FLP app modes), Design Compiler, Fusion Compiler, Timing Constraints Manager (previously FishTail), VCLP, Verdi, and CoreTools. Additionally, I am proficient in project support tools like Perforce, Git, Jira, and Confluence. Language Proficiency: My technical repertoire includes advanced skills in Verilog & System Verilog, Python, Perl, Tcl, and Shell scripting, enabling me to tackle complex engineering challenges with innovative solutions. My LinkedIn profile serves as a testament to a career dedicated to pushing the boundaries of ASIC/FPGA design and AI's transformative potential in engineering.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with a strong focus on ASIC/FPGA design and AI integration.

Location: Bengaluru, Karnataka, India

Experience: 3 yrs 11 mos

Skills

5g New Radio (nr)
Modems
Low Power
Vlsi
Logic Design
Documentation
Front-end Development

Career Highlights

Expert in ASIC/FPGA design and verification.
Proficient in AI-driven automation for design processes.
Experience with leading semiconductor companies like Nvidia and Qualcomm.

Work Experience

Qualcomm

Senior ASIC Design Engineer (1 yr 6 mos)

NVIDIA

ASIC Design Engineer II (11 mos)

Synopsys Inc

ASIC Design Engineer I (1 yr 6 mos)

Technical Intern (5 mos)

Honeywell Technology Solutions Lab Private Limited

Software Engineer Intern (2 mos)

SARCI.in

Business Automation Intern (9 mos)

Education

Bachelor of Engineering - BE at B. M. S. College of Engineering

PUC at Base Education

SSLC at Hymamshu Jyothi Kala Peetha

Bhargav S

Software Engineer

Bengaluru, Karnataka, India3 yrs 11 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

Expert in ASIC/FPGA design and verification.
Proficient in AI-driven automation for design processes.
Experience with leading semiconductor companies like Nvidia and Qualcomm.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with a strong focus on ASIC/FPGA design and AI integration.

Contact

Skills

Core Skills

5g New Radio (nr)ModemsLow PowerVlsiLogic DesignDocumentationFront-end Development

Other Skills

Formal VerificationSystemVerilogSpyglassVC SpyglassElectronic EngineeringSeleniumPythonJavaScriptAgentic AI DevelopmentGraphics Processing UnitComputer ArchitectureApplication-Specific Integrated Circuits (ASIC)Embedded C++Artificial Intelligence (AI)Digital Electronics

About

Experience

3 yrs 11 mos

Total Experience

1 yr 3 mos

Average Tenure

1 yr 6 mos

Current Experience

Qualcomm

Senior ASIC Design Engineer

Dec 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India · On-site

Designing Next Generation 5G Modems
Leveraging Agentic-AI to enhance Hardware Design and Verification

Modems5G New Radio (NR)

Nvidia

ASIC Design Engineer II

Jan 2024 – Dec 2024 · 11 mos · Bengaluru, Karnataka, India · On-site

As a member of the GPU Low Power Design and
Verification team at Nvidia, I held key
responsibilities across GPU product lines:
1. Low Power Design: Design system level logic for
implementing active and idle low-power features.
2. Formal Verification: Led the formal verification
effort for low-power features, power controls
connectivity, and power sequencing using
Synopsys VC Formal tool.
3. Power Aware Verification: Developed an
automated flow for dynamic verification of power
sequencing across all low-power features using
SystemVerilog assertions.
4. Workflow Automation: Automated system-level
design and connectivity flows using Python/Perl scripting.

Low powerVLSI

Synopsys inc

2 roles

ASIC Design Engineer I

Jul 2022 – Jan 2024 · 1 yr 6 mos · Bengaluru, Karnataka, India

As a part of the USB Design team, I was responsible for the following:
1. Design Ownership: I work on the Link and Protocol Adapter modules of the controller where I work on incremental design enhancements, simulation debug, assertion modelling and doc updates.
2. Tool Exposure: I have extensively worked on Spyglass and VC Spyglass tools for Lint, CDC and RDC enhancements. I maintain the controller's compliance with system-level RAL, synthesis tool flows, and Synopsys TCM tool. I have also been exposed to Synthesis tools like Design Compiler, Fusion Compiler and Power analysis tools like VCLP.
Apart from the technical exposure, I have also been trained on Soft Skills and am also an active volunteer in Nex-GEN ERG and CSR groups of Synopsys

Logic DesignDocumentation

Technical Intern

Feb 2022 – Jul 2022 · 5 mos · Bengaluru, Karnataka, India

As a part of the USB Design Team, I have learnt about CDC, RDC, and USB Specification and have also contributed to the development and enhancement of the USB 3.2 Controller. I have worked on Spyglass, VC Spyglass, and VC Formal Tools for Lint and CDC goals.

Logic DesignElectronic Engineering

Honeywell technology solutions lab private limited

Software Engineer Intern

Apr 2021 – Jun 2021 · 2 mos · Bengaluru, Karnataka, India

I worked on an IOT based project under the Connected Buildings branch of Honeywell Organisation. I automated the Smoke Testing of Samba Application using Selenium.

Front-End Development

Sarci.in

Business Automation Intern

Jul 2020 – Apr 2021 · 9 mos · Bengaluru, Karnataka, India

I worked on developing an autonomous software for parsing textual documents in any format (readable or non-readable) to extract necessary data fields.
It is built using a python backend and JavaScript based User-Interface. It can handle various kinds of document structures and has been rigorously tested.
The use cases include tax invoice parsing, bank document parsing and other company document parsing for automatic data entry.

Front-End Development