Abhijeet Sahu

Software Engineer

Bengaluru, Karnataka, India6 yrs 10 mos experience

Key Highlights

5+ years in Standard Cell Layout Design
Expertise in advanced technology nodes
Strong collaboration with design teams

Stackforce AI infers this person is a Semiconductor Layout Design Engineer with expertise in advanced nodes and physical design.

Contact

Skills

Core Skills

Standard Cell Layout DesignPhysical Design

Other Skills

ElectromigrationDesign Rule Checking (DRC)Layout Versus Schematic (LVS)ICC2DEMO MIQ FLOWFinFET technologyDemo MIQProgrammingC (Programming Language)C++Cadence VirtuosoVerilogInternet of Things (IoT)Low power vlsi designRTL Design

About

Layout development and designing of digital Professional with an experience of around 5+ years in the Standard Cell Library development and full custom layout. Experienced in Standard Cell layout design at multiple and advanced nodes. Overall domain knowledge of standard cells and latest QA methodology.

Experience

6 yrs 10 mos

Total Experience

Average Tenure

Current Experience

Synopsys inc

2 roles

Layout Design, Sr Engineer

Jan 2024 – Present · 2 yrs 5 mos

Layout development and designing of digital custom and standard cells for various node and foundries with utmost importance for the optimized area and quality layout.
Working nodes include TSMC (TS16, N4, N3, N3E, N2 N2P), INTEL, GF22FDX, Samsung (SS8, SS4, SS2), Rapidus.
Layout development and EM analysis for custom cells like Big drive inverters/Buffers.
Physical Verification (DRC, LVS, ERC, EM, DFM, Antenna).
Good understanding of deep sub-micron issues in layout design.
Architecture exploration for Base library, ECO & Level shifters.
Pin access, place and route evaluation of standard cell library using ICC2 tool.
Expertise in ICC2 & DEMO MIQ FLOW
Cross-Functional Collaboration with Design and Customer and delivering quality projects on scheduled time.

Standard cell Layout designElectromigrationPhysical DesignDesign Rule Checking (DRC)Layout Versus Schematic (LVS)ICC2+1

A&MS Layout Design Engr l

Aug 2021 – Jan 2024 · 2 yrs 5 mos

Designed standard cell layout on technologies - ( 2nm, 3nm, 4nm, 5nm,8nm,10nm ) in logic libraries team
Good knowledge on layout failure mechanism like Electro-migration ,Latch-up, IR drop, Antenna Effect
Developed different combinational , sequencial, level shifted & physical cells
Expertise in ICC2 and Demo miq
Work on Donut and hash design validation
Worked on advanced Finfet technology node

Standard cell Layout designElectromigrationFinFET technologyICC2Demo MIQPhysical Design