Sandesh kumar Sahu

Product Engineer

Madrid, Community of Madrid, Spain4 yrs 8 mos experience
Highly Stable

Key Highlights

  • 4+ years of experience in VLSI design verification.
  • Expertise in UVM and System Verilog methodologies.
  • Successful verification of complex designs in PCIe and 5G.
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in advanced verification methodologies.

Contact

Skills

Core Skills

Design Verification TestingFpga PrototypingMixed Signal Asic Verification

Other Skills

AMBA AXIAMBAPython (Programming Language)Universal Verification Methodology (UVM)PerlCode CoverageXilinx VivadoDigital DesignsVerilogSystemVerilog (SV)UVMzync 7000 series FPGA1x3 Router verificationLogic GatesTest Execution

About

I have a B.Tech degree in Electronics and Communications Engineering from GIET, Gunupur, and I am a Design Verification Engineer at Apple(independent contractor), a leading organization in Tech field. With 4 +years of experience and passion for VLSI design, I verify complex designs using cutting-edge verification methodologies, such as UVM, System Verilog, and various protocols and EDA tools. I have successfully completed and led several verification projects in the domains of PCIe, Ethernet, Networking, and 5G, demonstrating my technical expertise and problem-solving skills. For instance, I verified a 100G Ethernet Switch, and a Lowphy IP, using Questasim and Xcelium, and achieving high coverage and performance. I enjoy working in dynamic environments and contributing to the success of the team and the organization. I am always eager to learn new skills and technologies, and to collaborate with other VLSI design and verification enthusiasts. Let's connect and explore opportunities to work on exciting and innovative projects in the field of VLSI design and verification.

Experience

4 yrs 8 mos
Total Experience
1 yr 7 mos
Average Tenure
1 yr 5 mos
Current Experience

Exceltic

Design Verification Engineer

Jan 2025Present · 1 yr 5 mos · Madrid · On-site

  • Contributed to FPGA prototyping efforts, enhancing design robustness and ensuring functional excellence.
  • Modernized legacy testbenches, integrating advanced verification capabilities to improve validation processes.
  • Managed Cadence VIPs to streamline workflows, optimizing efficiency in design verification tasks.
AMBA AXIAMBADesign Verification TestingFPGA Prototyping

Semtech

Design Verification Engineer

Aug 2024Nov 2024 · 3 mos · Hyderabad · On-site

  • Verified a Mixed Signal ASIC chip to ensure optimal performance and reliability.
  • Upgraded legacy testbenches from VHDL to UVM, enhancing testing efficiency and maintainability.
Python (Programming Language)Universal Verification Methodology (UVM)Mixed Signal ASIC Verification

Vvdn technologies

2 roles

Design Verification Engineer

May 2023Aug 2024 · 1 yr 3 mos · On-site

PerlCode Coverage

Design Verification Engineer

Aug 2021May 2023 · 1 yr 9 mos · On-site

  • Collaborated with Firmware, DSP, and Design teams to validate digital designs effectively.
  • Developed strong problem-solving skills while addressing design verification challenges.
PerlXilinx Vivado

Maven silicon

Design Verification Trainee

Nov 2020Aug 2021 · 9 mos · Bengaluru

  • Gained hands-on experience in design verification as a trainee at Maven Silicon.
  • Developed proficiency in Verilog, SystemVerilog (SV), UVM, and Perl.
  • Contributed to demo projects, including 1x3 Router verification and RAM memory verification.
Code CoverageDigital Designs

Citta

Software Development Intern

Sep 2019Feb 2020 · 5 mos · Ahmedabad, Gujarat, India

  • . NET development

Education

GIET University Gunupur

Bachelor of Technology

Jan 2016Jan 2020

Kendriya Vidyalaya

Schooling

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