shakti singh

Software Engineer

Dhanbad, Jharkhand, India3 yrs 5 mos experience

Highly Stable

Key Highlights

Proficient in RTL Design and Verilog programming.
Strong analytical skills in digital design.
Experience in ASIC development and testing.

Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC development.

Contact

Skills

Core Skills

Rtl Design

Other Skills

VerilogEngineering DocumentationAnalytical SkillsSystemVerilogTest PlanningApplication-Specific Integrated Circuits (ASIC)Digital DesignsUniversal Verification Methodology (UVM)

Experience

3 yrs 5 mos

Total Experience

3 yrs 5 mos

Average Tenure

3 yrs 5 mos

Current Experience

Synopsys inc

3 roles

Sr. ASIC Digital Design Engineer

Dec 2024 – Present · 1 yr 6 mos

ASIC Digital Design Engineer

Oct 2023 – Dec 2024 · 1 yr 2 mos

Technical Intern

Jan 2023 – Oct 2023 · 9 mos

RTL DesignVerilog

Education

Indian Institute of Technology, Mandi

Master's degree — VLSI design

Jul 2021 – Jul 2023

Chaibasa engineering college Jharkhand

Bachelor's degree — Electrical engineering

Jul 2017 – Jul 2021

Indian School of learning Dhanbad Jharkhand

12th — PCM

Feb 2016 – Apr 2017

Indian school of learning Dhanbad Jharkhand

10th

Mar 2014 – Apr 2015

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