Apr 2026 – Present · 2 mos

Nov 2021 – Apr 2023 · 1 yr 5 mos

• Investigate the checks in the build flow which are performed manually or require customization and develop automated algorithms for them.
• Work on further automation to streamline the Build process.

Nov 2019 – Nov 2021 · 2 yrs

• QA, verification and build of ASIC semiconductor IP products, DDR and HBM PHYs.
• Working with the JIRA tool for reporting bugs and violations.
• Develop and support Build-related automated tasks for current and new types of DDR/HBM PHYs.

Jun 2017 – Nov 2019 · 2 yrs 5 mos

• Verification and build of analog, mixed-signal, and/or ASIC semiconductor IP products, DDR PHYs.
• The build process considers QA and verification, data collection, and release notes generation.
• The QA process includes DRC/LVS verification, PHY functional verification, consistency checking and related sub-stacks.
• Coretools setup, verification and generation for DDRn products

Jun 2016 – May 2017 · 11 mos

• Component build of DDR PHYs which considers data collection, release notes generation and QA.
• PHY functional verification.