Bharath R

Software Engineer

Bengaluru, Karnataka, India2 yrs 2 mos experience
Most Likely To Switch

Key Highlights

  • Expert in VLSI Timing Analysis and Closure.
  • Published IEEE paper on HBM3 architectural checks.
  • Delivered multiple tape outs with zero timing issues.
Stackforce AI infers this person is a Semiconductor VLSI Engineer with expertise in timing analysis and physical design.

Contact

Skills

Core Skills

Very-large-scale Integration (vlsi)Static Timing Closure

Other Skills

Timing AnalysisRC ExtractionSTA flowECO activitiesTCLSynopsys PrimetimeLogic SynthesisETMstar RcPerlSynopsys IC CompilerVerilogphyical design

About

To summarize myself, i'm a quick learner and a self motivated person. Iam a VLSI Timing Engineer.

Experience

2 yrs 2 mos
Total Experience
1 yr 1 mo
Average Tenure
1 yr 11 mos
Current Experience

Synopsys inc

2 roles

ASIC Physical Design Sr Engineer

Jul 2024Present · 1 yr 11 mos · Bengaluru

  • Part of sign-off Timing analysis, timing ECO generation, and POST-PNR implementation for 2 nm
  • and 4 nm.
  • Drove DMSA-based setup/hold fixes, constraints cleanup and skew/latency checks for advanced
  • memory architectures like HBM and UCIe programs.
  • Provided hands-on feedback to PnR and CTS teams to resolve the critical path and clock issues
  • in overall blocks.
  • Responsibilities include Timing Analysis in the UCIe architecture, RC Extraction, STA flow and
  • extracted timing models and ECO activities.
  • Automated STA analysis using tcl scripts to minimize manual effort.
  • Published an IEEE publication on the HBM3 architectural Specific checks and Timing Closure
  • (Internship Work).
  • Played a key role in delivering multiple tape outs with zero timing-related issues at signoff.
  • Executed QA sanity checks on timing libraries using Synopsys Primetime, ensuring error-free
  • deliverables to customers.
static timing closureVery-Large-Scale Integration (VLSI)Timing AnalysisRC ExtractionSTA flowECO activities+2

Intern

Dec 2023Jul 2024 · 7 mos · Bengaluru

Cognizant

Engineer trainee

Mar 2022Jun 2022 · 3 mos · Bangalore

Defence research and development organisation (drdo)

Internship Trainee

Mar 2021Mar 2021 · 0 mo · Bengaluru, Karnataka, India

  • The VHDL programming of FPGA boards at industry level at it's best. The testing of the microwave Antennas was the best experience till now. VHDL coding of the I2C controller for the electronic warfare system is the ongoing project.

Shridhan automation, india

Student Intern

Jan 2020Feb 2020 · 1 mo · Bengaluru, Karnataka, India

  • The overall basic anaytics of industrial automation was experienced. The calibration of magnetic levelling swithes was the amazing work I have experienced during the internship.

Hindustan aeronautics limited

Student Internship

Jan 2020Feb 2020 · 1 mo · Bengaluru, Karnataka, India

  • A very well experienced in overhaul division. learned the concepts of servicing all the aircrafts, overall information about the concepts of the parts had studied very well.

Education

Amrita School of Engineering, Bangalore

Master of Technology - MTech — VLSI DESIGN

Sep 2022Jul 2024

MVJ College of Engineering, Bangalore, India

Bachelor of Engineering - BE — Electronics and Communications Engineering

Jan 2017Jan 2021

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