Abhijeet Gavhane — Software Engineer
Good understanding of the ASIC and FPGA verification flow. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using industry standard EDA tools for the front-end design and verification
Stackforce AI infers this person is a Silicon Design Engineer with expertise in ASIC and FPGA verification.
Location: Hyderabad, Telangana, India
Experience: 9 yrs 10 mos
Skills
- Universal Verification Methodology (uvm)
- Systemverilog
Career Highlights
- Strong expertise in ASIC and FPGA verification.
- Proficient in SystemVerilog and UVM methodologies.
- Experienced in using industry-standard EDA tools.
Work Experience
AMD
Silicon Design Engineer 2 (4 yrs 3 mos)
Xilinx
Design Engineer 2 (1 yr 11 mos)
Mirafra Technologies
Verification Engineer II (11 mos)
Juntran Technologies Pvt Ltd
Verification Engineer II (1 yr 2 mos)
Semidigit Technology Pvt Ltd
Verification Engineer I (1 yr 7 mos)
Education
BE - Bachelor of Engineering at M.G.M's Jawaharlal Nehru College of Engineering, N-6, Cidco.Aurangabad,Maharshtra
